D/A Conversion with Asymmetrical PWM for Higher Dynamic Range
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Solution Overview
Problem
Conventional D/A conversion devices require increased operation clock frequency to enhance dynamic range, leading to higher power consumption and cost, especially in electronic musical instruments, limiting the resolution of pulse signals and integrity with quantizers.
Innovation Solution
A digital-to-analog conversion device that performs integration processing, first quantization processing, and output processing to generate asymmetrical pulse width modulation signals, allowing for increased dynamic range without increasing the operation clock frequency by using a correction value signal to adjust pulse shapes, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the operation clock frequency is increased to enhance dynamic range, then the quantization resolution is improved, but the power consumption increases
Solution Approach 1:
The patent applies asymmetry by generating pulse signals with asymmetrical duty ratios instead of symmetrical ones. The pulse width modulation section creates pulses where the high-level period does not equal the low-level period within each clock cycle, enabling more quantization stages (9 stages) to be achieved within the same clock frequency, thereby doubling the dynamic range without increasing power consumption
Solution Approach 2:
The patent changes the parameter of pulse signal characteristics from symmetrical to asymmetrical duty ratios. By modifying the pulse waveform parameters (making them asymmetrical), the system achieves higher quantization resolution (9 stages vs. 5 stages) at the same operation clock frequency, resolving the contradiction between resolution and power consumption
2Measurement precision
If the operation clock frequency is increased to enhance dynamic range, then the quantization stages are increased, but the device complexity increases
Solution Approach 1:
The patent uses asymmetrical pulse width modulation to achieve 9 quantization stages without increasing clock frequency or adding complex hardware. The asymmetrical duty ratio approach allows more quantization levels to be encoded within the same time period, increasing precision while maintaining simple device architecture
Solution Approach 2:
The patent utilizes periodic pulse width modulation at the existing clock frequency to achieve higher quantization stages. By varying the duty ratio periodically across different clock cycles and using asymmetrical pulses, the system encodes more information (9 stages) without requiring faster clocking or additional complex components
3Stability of the object's composition
If symmetrical pulse width modulation is used, then the pulse shape is symmetrical to the center point, but the quantization resolution is limited to half the number of clocks
Solution Approach 1:
The patent directly applies asymmetry by designing pulse signals with asymmetrical duty ratios where the high-level period differs from the low-level period. This asymmetrical approach enables the system to achieve 9 quantization stages by effectively utilizing both halves of the clock period, doubling the resolution compared to symmetrical PWM which is limited to half the number of clocks
Data Source
AI summary
A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.