D/A Converter Cyclic Current Cell Activation
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Solution Overview
Problem
Existing D/A converters face challenges with significant integral and differential non-linearity errors, particularly due to variations in reference currents, which limit their accuracy and resolution, especially in semiconductor processes where precise matching of current cells is not prioritized, resulting in suboptimal performance for high-bit resolution applications.
Innovation Solution
A D/A converter design that allocates 2N−1 current cells across multiple sections, with a cyclic activation and deactivation scheme managed by a decoder, ensuring that the number of continuously activated cells is limited to minimize error accumulation from reference current variations, and employing point symmetry in cell selection to enhance non-linearity error reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple D/A converter sections are used with reference currents, then the conversion range is improved, but integral non-linearity errors increase due to reference current variations
Solution Approach 1:
The patent divides the D/A converter into multiple sections (first to M-th D/A converter sections), each with a subset of current cells. This segmentation allows the conversion range to be expanded across sections while limiting the number of continuously activated cells within each section, thereby reducing error accumulation from reference current variations.
Solution Approach 2:
The patent changes the activation pattern parameter by implementing a cyclic activation scheme where current cells are activated in a specific sequence across sections rather than simultaneously. This parameter change ensures that the number of continuously activated cells is limited, reducing integral non-linearity errors while maintaining the extended conversion range.
2Measurement precision
If current cells are activated sequentially across sections, then differential non-linearity errors are reduced, but device complexity increases
Solution Approach 1:
The patent implements periodic action through cyclic activation of current cells across D/A converter sections. The decoder activates cells in a repeating cycle pattern, which reduces differential non-linearity errors by ensuring systematic distribution of activation while maintaining manageable device complexity through the regular periodic structure.
3Measurement precision
If the number of current cells is increased for higher resolution, then measurement precision is improved, but error accumulation from reference current variations increases
Solution Approach 1:
The patent segments the total current cells into multiple D/A converter sections, distributing the resolution requirement across sections rather than concentrating all cells in one section. This segmentation increases resolution while limiting error accumulation within each section by restricting the number of continuously activated cells.
Solution Approach 2:
The patent applies partial action by not activating all current cells simultaneously across all sections, but rather activating them cyclically and partially at any given time. This approach achieves the required resolution through sequential partial activation while preventing excessive error accumulation that would occur with full simultaneous activation.
Data Source
AI summary
A high accuracy D/A converter includes D/A converter sections including 64 current cells for outputting a current corresponding to 1 LSB of 8-bit input data and a D/A converter section including 63 current cells, a reference current generating section for supplying the respective D/A converter sections with reference currents, and a decoder for activating each of the current cells from the D/A converter sections to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is increased, and deactivating one each of the activated current cells from the D/A converter section to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is decreased.