D/A Decoder Circuit Using PMOS/NMOS Switches to Cut Transistor Count
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Solution Overview
Problem
Conventional digital to analog (D/A) converters used in display drivers, such as those for LCDs, require a high number of transistors, leading to increased power consumption and space occupancy, which is undesirable in modern, miniaturized electronic devices.
Innovation Solution
The use of P-type and N-type transistor switches instead of conventional CMOS switches, with an n-1 bit decoder formed using PMOS and NMOS transistors respectively, to reduce the overall transistor count and achieve efficient digital to analog conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS switches are used in D/A converters, then reliable digital to analog conversion is achieved, but transistor count increases leading to higher power consumption and larger area
Solution Approach 1:
The patent segments the D/A converter into two independent functional blocks: a digital-to-analog converter block and a level shifter block. This segmentation allows each block to be optimized independently, reducing the overall transistor count while maintaining conversion reliability. The DAC block handles the core conversion function with minimized transistors, while the level shifter handles voltage level adaptation separately.
Solution Approach 2:
The patent extracts the level shifting function from the main D/A conversion path and places it in a separate block. This extraction removes unnecessary transistors from the critical conversion path, reducing power consumption and transistor count while preserving the essential digital-to-analog conversion functionality through dedicated DAC circuitry.
2Measurement precision
If more transistors are used in D/A converters, then conversion precision is improved, but power consumption and area occupancy increase
Solution Approach 1:
The patent applies local quality by using different transistor configurations in different parts of the circuit. The DAC block uses a minimal transistor configuration sufficient for precise conversion, while the level shifter block uses a different configuration optimized for voltage adaptation. This localized optimization maintains precision where needed while reducing power consumption in auxiliary functions.
Solution Approach 2:
The patent changes the operating parameters of the transistors by separating the conversion and level-shifting functions. This parameter separation allows the DAC transistors to operate at optimal precision parameters with lower current, while the level shifter operates at different parameters optimized for voltage transformation, overall reducing power consumption while maintaining analog output precision.
3Adaptability or versatility
If conventional D/A converter design is used, then adequate conversion capability is provided, but device area and power consumption are excessive for miniaturized displays
Solution Approach 1:
The patent performs preliminary action by pre-configuring the DAC block with a compact transistor arrangement that is optimized for minimal area. The level shifter block is also pre-designed with an efficient topology that reduces area occupancy. This preliminary optimization of the circuit architecture enables the converter to maintain display driver compatibility while occupying significantly less area than conventional designs.
Solution Approach 2:
The patent transitions from a monolithic D/A converter design to a modular two-block architecture, effectively adding a dimensional aspect to the design. This modular approach allows independent optimization of each block's area efficiency while maintaining overall conversion capability compatible with various display drivers, reducing total footprint through spatial separation of functions.
Data Source
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AI summary
An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.