Time-Multiplexed DAC/ADC Sharing in Storage-Compute Chips
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Solution Overview
Problem
The existing storage and calculation integrated chips require large areas for high-precision digital-to-analog conversion circuits (DACs) and analog-to-digital conversion circuits (ADCs), leading to area waste and cost overhead due to the need for each input end to be connected to a DAC and each output end to be connected to an ADC.
Innovation Solution
A multiplexing device that shares DAC and ADC units through time division multiplexing, utilizing a combination of multiplexer modules and switch transistors to dynamically select and connect signals, reducing the number of components and circuit area by allowing multiple input ends to share DACs and multiple output ends to share ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each input end is connected to a DAC and each output end is connected to an ADC, then signal conversion precision is improved, but chip area and cost increase significantly
Solution Approach 1:
Multiple DACs and ADCs are merged into shared resources through time-division multiplexing. The patent combines N input ends sharing M DACs (where M < N) and N output ends sharing M ADCs, reducing the total number of conversion circuits while maintaining signal conversion precision through coordinated switching control.
Solution Approach 2:
Each DAC and ADC is designed to serve multiple functions by handling signals from multiple input ends or to multiple output ends through time-division multiplexing. The universal conversion circuits can dynamically switch between different signal paths, allowing one DAC/ADC to perform the function of multiple dedicated circuits.
2Adaptability or versatility
If each input end is connected to a DAC and each output end is connected to an ADC, then signal conversion capability is improved, but device complexity and cost overhead increase
Solution Approach 1:
The patent merges multiple independent DAC and ADC units into shared conversion circuits that serve multiple input and output ends. By combining N input ends with M DACs and N output ends with M ADCs through time-division multiplexing, the overall device complexity is reduced while preserving full signal conversion capability across all interfaces.
Solution Approach 2:
The system employs dynamic switching control to allocate shared DACs and ADCs to different input/output ends based on real-time signal conversion needs. The multiplexers and switch transistors dynamically reconfigure the signal paths, allowing the same conversion circuits to adaptively serve different functions at different time intervals.
3Measurement precision
If multiple DACs and ADCs are used for each input and output end, then conversion precision is maintained, but integration efficiency decreases
Solution Approach 1:
The patent merges multiple DAC and ADC units into shared conversion circuits that are jointly controlled through time-division multiplexing. This consolidation reduces the total component count and improves integration efficiency while maintaining conversion precision through coordinated switching that ensures each signal path receives dedicated conversion resources at appropriate time intervals.
Data Source
AI summary
A multiplexing device for a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a storage and calculation integrated chip, comprising a digital-to-analog conversion circuit (DAC) module, an analog vector-matrix multiplication operation circuit(AMAC) module, an analog-to-digital conversion circuit(ADC) module, a first many-to-one multiplexer (M1-MUX) module, a second M1-MUX module, a first one-to-many multiplexer (1M-MUX) module, a second 1M-MUX module, and a switching transistor module. At an AMAC input end, each DAC corresponds to a plurality of input ends and is shared with the first 1M-MUX module in a time multiplexing mode by means of the first M1-MUX module; at an AMAC output end, each ADC corresponds to a plurality of output ends, and is shared with the second 1M-MUX module in a time multiplexing mode by means of the second M1-MUX module; the number of DACs and ADCs is reduced, and the chip area is reduced.