DAC Cell Switching to Balance Aging Stress Over Time

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Solution Overview

Problem

High-performance DACs in nanometer CMOS technologies suffer from transistor aging and stress effects, leading to performance degradation due to mismatched transistor characteristics, especially in differential paths or converter cells, which cannot be effectively mitigated by conventional techniques without overdesigning the circuit or introducing significant overhead.

Innovation Solution

Implementing a controller to periodically change the operating conditions of DAC cells, balancing stress and aging effects by alternating the active set of DAC cells, using low-frequency clock signals during standby modes, and swapping inactive cells to maintain output consistency, thereby reducing NBTI stress and maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional techniques (guard-banding, additional circuitry) are used to mitigate stress and aging effects, then reliability is improved, but device complexity and power consumption increase significantly

Engineering Contradiction:
ImproveDAC performance stabilityVSAvoidcircuit overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the DAC circuit configuration changeable over time. Specifically, the differential paths are dynamically switched between active and inactive states according to a periodic signal, allowing the circuit to adapt its operating conditions to mitigate stress effects. This dynamic reconfiguration enables the same hardware to operate in different modes (normal operation vs. stress mitigation) without adding permanent overhead circuitry.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action by applying a periodic signal to alternately activate and deactivate different differential paths in the DAC. This periodic switching creates alternating stress conditions on matched transistor pairs, ensuring they experience similar cumulative stress over time. The periodic nature of this action allows the circuit to self-balance stress effects without requiring continuous monitoring or control overhead.

Inventive Principle:
Principle #19Periodic action

2Reliability

If guard-banding is applied to account for threshold voltage shifts, then reliability is improved, but productivity decreases due to reduced effective frequency

Engineering Contradiction:
Improvetiming specification complianceVSAvoideffective operating frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the operating parameters of the DAC circuit by periodically altering which differential paths are active. Instead of statically lowering the operating frequency to account for aging (guard-banding), the system dynamically changes the activation state of circuit paths based on a periodic signal. This parameter change approach allows the circuit to maintain higher effective frequencies while still mitigating stress effects through alternating activation patterns.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If single-ended switch-off is used to relax stress effects, then reliability is improved, but device complexity increases due to complicated circuitry

Engineering Contradiction:
Improvestress effect mitigationVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the existing differential path switching circuitry serve multiple functions: it performs its normal signal routing function during active operation and simultaneously performs stress mitigation by periodically deactivating paths according to a periodic signal. This multi-functionality allows the same hardware to achieve both signal processing and reliability improvement without adding dedicated stress-mitigation circuitry, thereby avoiding increased device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12407354B2Digital-to-analog converter and a method for reducing aging effects on components of the digital-to-analog converter
Publication Date: 2025.09.02 INTEL CORP
  • US12407354B2 patent drawing
  • US12407354B2 patent drawing
  • US12407354B2 patent drawing

AI summary

A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.