Asymmetrical PWM D/A Conversion Without Higher Clock Frequency
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Solution Overview
Problem
Conventional D/A conversion devices require increased operation clock frequency to enhance dynamic range, leading to higher power consumption and cost, especially in electronic musical instruments, limiting the resolution of pulse signals and integrity of quantization.
Innovation Solution
A digital-to-analog conversion device that performs integration processing, first quantization, and output processing to generate asymmetrical PWM signals, allowing for increased quantization stages without increasing the operation clock frequency, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the operation clock frequency is increased to enhance dynamic range, then the dynamic range is improved, but the power consumption increases
Solution Approach 1:
The patent applies asymmetry by generating asymmetrical PWM signals where the pulse width is not symmetric around the center of the processing period. This asymmetrical pulse generation allows for increased quantization stages and dynamic range without requiring higher clock frequencies, thereby resolving the contradiction between dynamic range improvement and power consumption increase.
Solution Approach 2:
The patent changes the parameter of pulse signal symmetry from symmetrical to asymmetrical, and introduces correction values to adjust the asymmetry. This parameter change enables the system to achieve higher dynamic range with the same operation clock frequency, avoiding the need to increase clock frequency and thus preventing power consumption increase.
2Measurement precision
If the operation clock frequency is increased to enhance dynamic range, then the dynamic range is improved, but the device complexity increases
Solution Approach 1:
By utilizing asymmetrical PWM signal generation with correction values, the patent achieves higher dynamic range without increasing clock frequency or adding complex hardware components, thus resolving the contradiction between dynamic range improvement and device complexity increase.
Solution Approach 2:
The patent achieves dynamic range enhancement through parameter changes in the PWM signal generation process rather than through hardware complexity increases, maintaining simplicity while improving performance.
3Measurement precision
If the operation clock frequency is increased to enhance dynamic range, then the dynamic range is improved, but the cost increases
Solution Approach 1:
The asymmetrical PWM generation method with correction values enables dynamic range improvement without requiring higher frequency components or more complex circuitry, thereby avoiding cost increases associated with high-frequency PLL circuits and other expensive components.
Solution Approach 2:
By changing the approach from frequency-based dynamic range enhancement to asymmetry-based enhancement, the patent avoids the need for expensive high-frequency components, resolving the contradiction between dynamic range improvement and cost increase.
Data Source
AI summary
A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.