High-Speed DAC Back-Gate Biasing for Linearity and Power Scaling
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Solution Overview
Problem
High-speed data converters face performance degradation due to process corner variations and cell mismatches, leading to increased costs and time-to-market, as existing calibration methods require extra chip area and power, and struggle with granular control of back-gate bias voltage.
Innovation Solution
A high-speed digital-to-analog converter (DAC) system utilizing adaptive back-gate biasing with a programmable back-gate bias generator, allowing independent or collective adjustment of back-gate bias voltages for reference current cells and current source arrays, enabling efficient power scaling and reduced supply voltage without compromising accuracy or speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration methods are used to achieve desired performance, then resolution and linearity are improved, but chip area and power consumption increase
Solution Approach 1:
The patent extracts the calibration function from external production testing and implements it through integrated back-gate bias control circuits within the DAC architecture. This allows calibration to be performed internally using the back-gate terminals of transistors, eliminating the need for external calibration hardware and reducing chip area while maintaining resolution and linearity performance
Solution Approach 2:
The patent changes the electrical parameters (back-gate bias voltages) of existing transistors to achieve calibration and compensation effects. By adjusting the back-gate bias voltages of reference current cell transistors and unit cell transistors independently, the system can correct gain errors and offset errors without adding calibration hardware, thus reducing power consumption while maintaining measurement precision
2Adaptability or versatility
If separate deep N-well isolation is used for each segment, then threshold voltage tuning is enabled, but chip area increases
Solution Approach 1:
The patent merges the threshold voltage tuning function into a unified back-gate bias control architecture that can be applied to all segments simultaneously. Instead of requiring separate deep N-well isolation for each segment, the system uses common back-gate bias control circuits that can independently adjust the threshold voltages of reference current cell transistors and unit cell transistors across all segments, significantly reducing chip area while maintaining tuning capability
Solution Approach 2:
The back-gate bias control mechanism serves multiple functions: it enables threshold voltage tuning for all segments, provides gain error compensation, and allows offset error correction. This universal control mechanism eliminates the need for separate isolation structures for each segment, achieving adaptability without increasing chip area
3Manufacturing precision
If granular control of back-gate bias voltage is implemented, then segment mismatch is reduced, but control complexity increases
Solution Approach 1:
The patent segments the back-gate bias control into two independent control paths: one for reference current cell transistors and another for unit cell transistors. Each path has its own control circuitry that can independently adjust the back-gate bias voltages. This segmentation allows granular control of segment matching while keeping control complexity manageable by avoiding the need for individual control of every transistor
Solution Approach 2:
The system changes the back-gate bias voltage parameters to compensate for segment mismatches. By independently adjusting these voltage parameters through dedicated control circuits, the system achieves precise segment matching without requiring complex control mechanisms, as the parameter adjustment approach is inherently simpler than structural modifications
Data Source
AI summary
A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (“BBGEN”). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (“BBGEN”) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.