DAC Current Mirror Biasing to Cut Chip Area and Glitches
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face challenges with large chip area and high cost due to the need for numerous components and complex calibration, particularly in hybrid binary and thermometer-coded designs, which compromise on glitch performance and require extensive transistor sizes.
Innovation Solution
The solution involves scaling transistor biasing voltages instead of sizes to achieve weighted currents, using a current mirror circuit to control gate bias voltages and reduce the number of transistor legs, thereby minimizing chip area and cost while maintaining effective conversion performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermometer coded DAC is used, then glitch performance is improved, but chip area increases
Solution Approach 1:
The patent divides the thermometer-coded DAC into multiple sub-DACs, each handling a portion of the input bits. This segmentation reduces the number of current sources required in each sub-DAC while maintaining overall resolution and glitch performance through parallel operation and proper current summation.
Solution Approach 2:
The patent changes the operating parameters of the current sources by applying different bias voltages to achieve weighted current outputs. By varying the bias voltage parameters rather than changing transistor sizes, the patent reduces area while maintaining the weighted binary functionality needed for efficient conversion.
2Area of stationary object
If binary weighted DAC is used, then chip area is reduced, but glitch performance deteriorates
Solution Approach 1:
The patent segments the binary-weighted structure into multiple smaller binary-weighted sub-DACs that operate in parallel. Each sub-DAC handles a portion of the input range, reducing individual transistor sizes and improving glitch performance while maintaining compact area through efficient current summation.
Solution Approach 2:
The patent applies different bias voltage parameters to the current sources in the binary-weighted structure to achieve proper weighting without requiring large transistor size variations. This parameter-based weighting improves linearity and reduces calibration requirements while maintaining area efficiency.
3Measurement precision
If hybrid binary and thermometer-coded DAC is used, then conversion accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the hybrid DAC into separate binary-weighted and thermometer-coded sub-DACs, each optimized for specific input ranges. This segmentation allows each sub-DAC to use the most appropriate structure for its function, simplifying the overall design while maintaining high conversion accuracy through coordinated operation.
Solution Approach 2:
The patent uses bias voltage parameter changes to control the weighting and operation of different sub-DACs, enabling smooth transitions between binary and thermometer coding modes. This parameter-based control reduces the complexity of switching mechanisms and calibration requirements while maintaining conversion accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces transistor size and chip area, leading to cost savings and improved conversion efficiency by maintaining equivalent conduction currents with fewer and smaller transistors, thus addressing the limitations of conventional DACs.
Implementation Method 1
The current mirror circuit receives a reference current and provides scaled versions of this current to multiple output nodes. By controlling the gate bias voltages of the transistors in the current mirror, the patent achieves weighted current outputs where I0, I1, I2, and I3 represent progressively larger weighted currents without requiring proportional increases in transistor physical sizes.
Data Source
AI summary
This invention discloses a digital to analog converter (DAC) for converting a digital signal with a predetermined number of bits to a corresponding analog signal, the DAC comprises a first current source element having a first control signal, the first control signal controlling the conduction current provided by the first current source element, and a second current source element having a second control signal, the second control signal controlling the conduction current provided by the second current source element, wherein the first and the second control signals have different voltages during operation of the DAC.