DAC Bit-Swapping Control for Constant Binary Transition Rate
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Solution Overview
Problem
DACs in applications like RF and SerDes suffer from amplitude and timing errors that lead to distortion and limit spurious-free dynamic range (SFDR), particularly in low-amplitude signals, due to strong signal dependence and random switching.
Innovation Solution
Implementing a system with a multiplexer and controller to swap bits of digital and dither values, using random dither signals to randomize LSBs code and maintain a constant binary transition rate (BCTR), thereby reducing errors and noise without affecting the desired output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If random dither signals are used to randomize LSBs code, then amplitude and timing errors are reduced, but random switching increases causing supply modulation and noise
Solution Approach 1:
The patent converts the harmful random switching noise into a beneficial constant transition pattern. By using a constant-weight code with fixed Hamming weight, the random dither signals still randomize the LSBs code to reduce amplitude and timing errors, but the constant transition rate converts the harmful random supply modulation into a controlled, predictable noise floor that can be filtered more effectively.
Solution Approach 2:
The patent changes the parameter of binary transition rate from variable (random) to constant. By employing a constant-weight code where each code word has the same number of transitions, the system maintains the randomization benefit for error reduction while eliminating the harmful variable supply modulation, transforming the noise characteristics into a more manageable form.
2Device complexity
If binary-weighted DAC architecture is used, then device complexity is reduced, but signal dependence causes distortion and limits SFDR
Solution Approach 1:
The patent segments the DAC architecture into a binary-weighted section and a dither injection section. The binary-weighted DAC handles the main conversion with low complexity, while a separate dither signal generator and constant-weight code encoder handle the randomization. This segmentation allows the system to maintain the simplicity of binary-weighted architecture while adding the SFDR improvement through dithering without full unary implementation.
Solution Approach 2:
The patent creates a composite coding scheme that combines binary-weighted code and constant-weight dither code. The final DAC input is a composite of the original binary signal and the randomized constant-weight dither signal, achieving both the area efficiency of binary-weighted DAC and the performance benefits of randomized coding to reduce signal dependence and improve SFDR.
3Manufacturing precision
If dither signals are injected to randomize code, then distortion is reduced, but in-band noise floor increases
Solution Approach 1:
The patent uses periodic dither signal injection at a frequency outside the signal band. By choosing a periodic dither frequency that is higher than the maximum signal frequency, the randomization benefit is achieved while the dither noise is pushed to out-of-band frequencies where it can be filtered, thus reducing in-band noise floor while maintaining distortion reduction.
Solution Approach 2:
The constant-weight code acts as an intermediary between the binary-weighted DAC and the dither signal. It transforms the dither signal into a form that randomizes the code transitions without directly adding high-frequency noise to the output, thereby reducing distortion while minimizing the increase in in-band noise floor through controlled transition rates.
Data Source
AI summary
A system may have a multiplexer and a controller. For a transition from a first pair of bits in first data provided to digital-to-analog converters (DACs) to a second pair of bits in second data, the controller may determine whether the transition is of a first type or of a second type, and in response to determining that the transition is of the first type, control the multiplexer to output the second pair of bits to the DACs. In response to determining that the transition is of the second type and the second pair of bits are to be swapped, the controller may control the multiplexer to output a swapped pair of bits to the DACs. Data output by the multiplexer based on the second data has a predetermined number of bits that have binary values different from those of corresponding bits in the first data.