DAC Capacitor Layout to Reduce Parasitic Capacitance
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Solution Overview
Problem
The existing capacitor layouts in SAR ADC ICs suffer from parasitic capacitance issues, leading to deviations in capacitance ratios and poor linearity, making them unsuitable for high-definition applications.
Innovation Solution
A capacitor layout design where capacitor groups are arranged such that those at the edge, which tolerate capacitance variance, are not dominant in determining bits, and those inside maintain accurate capacitance, eliminating the need for dummy capacitors and minimizing parasitic capacitance effects, with optional use of metal-insulation-metal or poly-insulator-poly capacitor units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If dummy capacitors are added around capacitor groups to ensure uniform circuitry density, then layout uniformity is improved, but parasitic capacitance between capacitor units increases
Solution Approach 1:
The patent removes dummy capacitors from the layout entirely. Instead of adding non-functional dummy capacitors around the functional capacitor groups, the design uses only functional capacitor groups with carefully controlled inter-group spacing, eliminating the source of parasitic capacitance while maintaining layout uniformity through proper positioning of the remaining capacitor groups.
Solution Approach 2:
The patent applies different spacing requirements to different regions of the layout. Capacitor groups are positioned with specific spacing distances from each other and from the layout boundaries, creating localized density control zones. This ensures uniform circuitry density without requiring dummy capacitors, as each region is optimized for its specific function.
2Area of stationary object
If capacitor groups are placed close together to increase circuit density, then area utilization is improved, but parasitic capacitance between groups increases
Solution Approach 1:
The patent optimizes the spacing parameter between capacitor groups to achieve an optimal balance. By carefully controlling the distance between adjacent capacitor groups and between capacitor groups and layout boundaries, the design minimizes parasitic capacitance while maintaining high area utilization. This parameter optimization allows compact layout without excessive parasitic effects.
3Device complexity
If edge capacitor groups are made functional instead of using dummy capacitors, then manufacturing complexity is reduced, but capacitance matching accuracy deteriorates
Solution Approach 1:
The patent assigns different functional roles to capacitor groups based on their positions. Edge capacitor groups are designed with the understanding that they will have different parasitic capacitance characteristics than internal groups. The design compensates for these position-dependent variations through careful selection of which groups are used for critical bit determinations, ensuring that groups requiring highest precision are placed in positions with most favorable parasitic characteristics.
Solution Approach 2:
The patent adjusts the capacitance values and spacing parameters of edge capacitor groups to compensate for their different parasitic environment. By modifying the nominal capacitance values and positioning parameters of edge groups relative to internal groups, the design achieves uniform effective capacitance across all functional groups despite their different locations and parasitic conditions.
Data Source
AI summary
The present invention discloses a capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), comprising a first capacitor group, a second capacitor group and a third capacitor group. The first capacitor group, located within an interior layout area of the capacitor layout, determines a most significant bit (MSB) of the DAC IC and includes a plurality of capacitor units coupled between a first upper circuit and a first lower circuit. The second capacitor group, located within the interior layout area, determines a non-MSB bit of the DAC IC and includes at least one capacitor unit(s) coupled between a second upper circuit and a second lower circuit. The third capacitor group includes a plurality of capacitor units coupled between a third upper circuit and a third lower circuit which are not short-circuited; the capacitor units of the third capacitor group are disposed around the interior layout area.