Digital-to-analog converter cascode cell segmentation
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Solution Overview
Problem
Current steering digital-to-analog converters face accuracy degradation due to increased parasitic capacitance caused by elongated metallic interconnects, leading to spike voltage and reduced output signal quality as the number of bits increases.
Innovation Solution
The digital-to-analog converter employs a cascode configuration for the current source, with transistors arranged in separate regions connected by metallic interconnects, stabilizing the voltage at node A and reducing parasitic capacitance, thereby maintaining output signal accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits increases, then the conversion precision is improved, but the metallic interconnects need to be elongated which increases parasitic capacitance and degrades output signal accuracy
Solution Approach 1:
The current source is divided into multiple current source transistors arranged in a matrix pattern across different regions of the semiconductor chip. This segmentation allows the interconnect length to be managed in smaller segments rather than requiring one long interconnect, thereby reducing total parasitic capacitance while maintaining high-bit conversion precision
Solution Approach 2:
The current source transistors are arranged in a two-dimensional matrix pattern across the chip rather than linearly. This spatial distribution in multiple dimensions reduces the maximum interconnect length required between any current source transistor and the differential switch, minimizing parasitic capacitance effects even as the number of bits increases
2Object-affected harmful factors
If metallic interconnects are elongated to connect current sources and differential switches in separate regions, then digital noise isolation is improved, but parasitic capacitance increases causing spike voltage and accuracy degradation
Solution Approach 1:
By segmenting the current source into multiple transistors distributed across different regions, the patent reduces the length of individual metallic interconnects needed to connect current sources to differential switches. This segmentation maintains digital noise isolation between regions while minimizing the parasitic capacitance generated by shorter interconnect paths
Solution Approach 2:
The patent applies different spatial arrangements to different components: current source transistors are distributed in a matrix pattern in one region while differential switches are positioned in another region. This local quality differentiation allows optimal placement that balances noise isolation with minimal interconnect length, reducing parasitic capacitance
Data Source
AI summary
According to one embodiment, a digital-to-analog converter includes a plurality of cells. Each cell includes a current source and a differential switch. The current source includes a first transistor arranged in a first region and connected to either a power source or a ground, a second transistor arranged in a second region which is different from the first region and connected directly or indirectly with the first transistor in a cascode configuration, and a metallic interconnect connecting the first region and the second region electrically. The differential switch includes a pair of transistors, each connected to the second transistor and arranged in the second region.