DAC Cell Sorting and Pointer Selection for Mismatch Shaping
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Solution Overview
Problem
Conventional dynamic element matching (DEM) techniques for multi-bit digital-to-analog converters (DACs) fail to optimally cancel mismatch errors, leading to performance degradation due to noise and distortion, as they either introduce large harmonic distortion or increase noise floor, thus degrading SNR/SFDR.
Innovation Solution
A digital-to-analog converter design that includes a mismatch error sorting circuit to generate a sorting result based on mismatch error levels, and a DEM circuit that shapes these errors, along with a pointer location selecting circuit that chooses new locations based on DAC cell utilization rates to improve error cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DEM techniques re-use DAC cells in opposite polarity to cancel mismatch errors, then mismatch error cancellation is achieved, but the distribution formed by mismatch errors is not optimal, leading to suboptimal mismatch-shaping ability
Solution Approach 1:
The patent applies preliminary action by pre-sorting DAC cells according to their mismatch error levels before the DEM operation. The sorting circuit characterizes each DAC cell's mismatch error and arranges them in a specific sequence (e.g., from lowest to highest error level). This preliminary sorting enables the DEM algorithm to systematically select and alternate between cells with opposite polarity and complementary error characteristics, optimizing the error cancellation and shaping performance rather than using random or fixed selection methods.
2Object-affected harmful factors
If a new pointer location is selected based on a fixed value, then noise floor is reduced, but large harmonic distortion is introduced, leading to worse SNDR/SFDR
Solution Approach 1:
The patent applies dynamics by making the pointer location selection adaptive rather than fixed. The pointer location is dynamically adjusted based on the sorted order of DAC cells and the current input signal characteristics. When the pointer needs to be updated, the system selects new locations based on the pre-established sorting sequence, which considers the mismatch error levels of different cells. This dynamic selection strategy ensures that both noise floor and harmonic distortion are optimized simultaneously.
3Object-generated harmful factors
If a new pointer location is selected based on a random value, then harmonic distortion is spread to noise, but noise floor increases, leading to worse SNR
Solution Approach 1:
The patent applies parameter changes by systematically varying the pointer location based on the sorted DAC cell indices rather than using random values. The sorting operation transforms the original cell indices into a new ordered sequence, and the pointer location is updated by incrementing or decrementing through this sorted sequence. This controlled parameter change ensures that pointer transitions follow a deterministic pattern that optimizes both noise floor and harmonic distortion distribution, avoiding the noise floor elevation caused by random selection.
Data Source
AI summary
A digital-to-analog converter (DAC) includes a plurality of DAC cells, a mismatch error sorting circuit, and a dynamic element matching (DEM) circuit. The mismatch error sorting circuit generates a sorting result of the plurality of DAC cells according to mismatch error levels of the plurality of DAC cells. The DEM circuit shapes the mismatch error levels of the plurality of DAC cells according to the sorting result of the plurality of DAC cells.