DAC Cell Rotation Control for Distortion and Switching Trade-Off
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Solution Overview
Problem
Conventional Dynamic Element Matching (DEM) approaches for Digital-to-Analog Converters (DACs) either optimize switching noise or harmonic distortion, but not both simultaneously, leading to extensive circuit complexity and unwanted noise shaping, while requiring low implementation complexity and low power consumption at high sampling rates.
Innovation Solution
A DAC design that uses a code converter circuit, bit-shifter circuit, and cell activation circuit to generate shift codes through DEM, allowing circular shifting of DAC cells with reduced rotation range to minimize harmonic distortion and switching activity, while maintaining simplicity and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DEM approaches optimize only switching noise or only harmonic distortion, then one parameter is improved, but the other remains unoptimized and circuit complexity increases
Solution Approach 1:
The patent implements dynamic element matching by dynamically selecting and switching between different DAC cells based on real-time error compensation requirements. The system adapts the activation of converter cells during operation to minimize harmonic distortion while managing switching activity, rather than using a fixed cell selection scheme.
Solution Approach 2:
The patent changes the operational parameters of DAC cells by varying their activation states and switching patterns. By controlling which cells are active and when they switch, the system optimizes the balance between harmonic distortion reduction and switching noise minimization, achieving both goals simultaneously through parameter optimization.
2Manufacturing precision
If DEM selects different sets of cells each time a code is requested to reduce systematic errors, then harmonic distortion is reduced, but switching activity increases leading to higher noise and power consumption
Solution Approach 1:
The patent applies partial element matching by selectively activating only the necessary number of DAC cells required to achieve the desired output code, rather than switching all cells or using excessive switching activity. This partial action approach reduces systematic errors and harmonic distortion while minimizing unnecessary switching events that generate noise.
Solution Approach 2:
The patent maintains continuous useful action by keeping certain DAC cells in a stable active state across multiple code requests when possible, reducing the frequency of switching events. The system continues to provide error compensation through DEM while minimizing disruptive switching activity that generates noise and consumes power.
3Productivity
If DEM algorithms run at high sampling rates to achieve low implementation complexity, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by updating DEM cell selections at optimized intervals rather than continuously at every sampling instant. The system performs element matching calculations periodically at rates that balance processing requirements with power consumption constraints, reducing the computational burden while maintaining effective error compensation.
Solution Approach 2:
The patent achieves multi-functionality by integrating the DEM algorithm implementation into the existing DAC control logic and digital signal processing pipeline. The same processing resources handle both the primary DAC conversion function and the DEM error compensation function, eliminating the need for separate dedicated hardware and reducing overall power consumption.
Data Source
AI summary
A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.