DAC Cell Charge Injection for Duty Cycle Error Correction
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Solution Overview
Problem
Digital to analog converters (DACs) face performance degradation due to duty cycle errors caused by mismatches in DAC cells, leading to harmonic distortion and reduced Signal-to-Noise-and-Distortion Ratio (SNDR) and spurious free dynamic range (SFDR), especially at high speeds, where existing solutions either fail to directly address the core issue of switching transistor mismatches or introduce additional distortion.
Innovation Solution
A correction circuit is implemented using a capacitive T-network charge pump that injects a small amount of charge opposite to the error charge at the low-impedance node of the DAC cell during data signal transitions, compensating for duty cycle errors and their collateral effects, while a calibration circuit measures and adjusts the correction based on observed errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more power hungry circuitry is used to reduce duty cycle errors, then duty cycle error is reduced, but power consumption increases
Solution Approach 1:
The patent extracts only the essential correction function by using a simple capacitive network to inject charge at the low-impedance node, separating the error correction function from the main DAC circuitry. This minimalistic approach corrects duty cycle errors without requiring complex, power-hungry correction circuits.
Solution Approach 2:
The patent changes the electrical parameters (charge amount and timing) at the low-impedance node to compensate for duty cycle errors. By injecting a small amount of charge (atto-Coulombs) at precise moments during data signal transitions, the system corrects errors without increasing overall power consumption.
2Reliability
If correction is applied at high-speed transitions, then duty cycle error is reduced, but distortion may be introduced
Solution Approach 1:
The patent uses the low-impedance node as an intermediary point for charge injection. This intermediary approach allows correction of duty cycle errors without directly interfering with the main signal path, thereby avoiding the introduction of additional distortion while maintaining high-speed operation.
Solution Approach 2:
The patent applies partial correction by injecting only the necessary amount of charge (atto-Coulombs) at specific moments during data transitions. This controlled, partial action corrects duty cycle errors without over-correcting or introducing excessive distortion to the signal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces duty cycle errors, improving the linearity and performance of high-speed DACs by injecting charge on the order of atto-Coulombs, thereby enhancing the SNDR and SFDR without introducing significant distortion.
Implementation Method 1
A correction circuit is implemented using a capacitive T-network charge pump that injects a small amount of charge opposite to the error charge at the low-impedance node of the DAC cell during data signal transitions
Data Source
AI summary
Digital to analog converter generates an analog output corresponding to a digital input by controlling DAC cells using bits of the digital input. The DAC cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the DAC cells may have duty cycle error or mismatches. To compensate for the duty cycle error of a DAC cell, a small amount of charge is injected into a low-impedance node of a DAC cell when the data signal driving the DAC cell transitions, or changes state. The small amount of charge is generated using a capacitive T-network, and the polarity of the charge injected is opposite of the error charge caused by duty cycle error. The opposite amount of charge thus compensates or cancels out the duty cycle error, and duty cycle error present at the output of the DAC cell is reduced.