DAC Charge Sharing Across Passive and Active Conversion Cycles
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Solution Overview
Problem
Existing Digital to Analog Converters (DACs) face a trade-off between space consumption due to parasitic capacitance in passive charge-sharing and high power consumption in active charge-sharing, making them inefficient for certain applications.
Innovation Solution
A method and system that alternates between passive and active charge-sharing in multiple cycles, using a switched capacitor array with a control signal generator to produce pulse-width control signals, allowing for efficient conversion of digital bits to analog voltages with reduced capacitor array size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If passive charge-sharing is used during conversion, then conversion speed is improved, but linearity deteriorates due to parasitic capacitance in switch circuitry
Solution Approach 1:
The patent segments the conversion process into two distinct phases: a first conversion cycle using passive charge-sharing for speed, and a second conversion cycle using active charge-sharing for linearity. This temporal segmentation allows each technique to operate in its optimal regime without compromising the other.
Solution Approach 2:
The patent changes the operational parameters of the charge-sharing mechanism by switching between passive and active modes. During the first cycle, passive charge-sharing parameters are used for fast conversion. During the second cycle, active charge-sharing parameters are engaged to correct linearity errors, effectively using parameter changes to resolve the contradiction.
2Manufacturing precision
If an active charge-sharing technique with op-amp negative feedback is used, then linearity is improved, but power consumption increases due to tight op-amp settling time requirements
Solution Approach 1:
The patent divides the conversion process into two cycles, using active charge-sharing only in the second cycle for linearity correction. This segmentation limits the duration of high-power operation, thereby reducing overall power consumption while still achieving the desired linearity improvement.
Solution Approach 2:
Instead of continuously applying active charge-sharing with full power, the patent applies it partially—only during the second conversion cycle when needed for linearity correction. This partial action approach achieves the necessary linearity improvement without the excessive power consumption that would result from continuous active charge-sharing.
3Manufacturing precision
If a large-sized capacitor array is added to accommodate passive charge-sharing, then linearity is improved, but die area increases
Solution Approach 1:
The patent segments the linearity improvement task between two approaches: passive charge-sharing with a compact capacitor array for the first cycle, and active charge-sharing for the second cycle. This segmentation allows the use of a smaller capacitor array than would be required if passive charge-sharing alone were used for the entire conversion process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-resolution analog signal generation with moderate power consumption and a smaller capacitor array, balancing linearity and efficiency by allocating more time for active charge-sharing on more significant bits.
Implementation Method 1
converting a first set of digital bits to a first analog voltage using passive charge-sharing
Data Source
AI summary
A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.