DAC Circuit Topology for Fewer MOS Transistors in Source ICs
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Solution Overview
Problem
The existing digital to analog conversion circuits in display panels require a large number of MOS transistors, leading to increased volume and cost of the source IC, as each channel needs a separate DAC module with numerous switching MOS transistors, which is inefficient and costly.
Innovation Solution
A digital to analog conversion circuit design that reduces the number of MOS transistors by using a configuration of first and second MOS transistors, resistors, and a capacitor, where the resistance of the resistors varies with digital bit power, allowing parallel connection of resistors to achieve nonlinear voltage variation, significantly reducing the number of transistors required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional DAC module is used for each channel to convert digital bits to analog voltage values, then the conversion accuracy and display quality are maintained, but the number of MOS transistors increases significantly, leading to larger chip volume and higher cost
Solution Approach 1:
The patent merges multiple DAC channels into a single integrated circuit structure where first MOS transistors handle digital bit signals and second MOS transistors handle row blank signals. This consolidation reduces the total number of transistors compared to having separate DAC modules for each channel, while maintaining conversion accuracy through the coordinated operation of these merged components.
Solution Approach 2:
The second MOS transistors serve multiple functions: they control row blank signals during display blanking periods and work in conjunction with first MOS transistors during display periods. This multi-functionality reduces the need for dedicated transistors for each function, thereby reducing overall device complexity while preserving conversion precision.
2Measurement precision
If the number of input bits in the DAC module is increased to improve display resolution, then the conversion precision is improved, but the number of MOS transistors increases exponentially, resulting in larger chip area and higher cost
Solution Approach 1:
The patent employs dynamic control where first MOS transistors are selectively turned on based on digital bit values during display periods, and second MOS transistors are activated during blanking periods. This dynamic operation allows the circuit to handle higher resolution inputs without requiring all transistors to be permanently active, thereby reducing the effective chip area needed for high-resolution conversion.
Solution Approach 2:
The circuit operates in periodic cycles between display periods and display blanking periods. During display blanking periods, second MOS transistors are turned on to reset or prepare the circuit state. This periodic action allows the system to process higher resolution data efficiently by utilizing time-division multiplexing, reducing the spatial area required compared to a continuously active high-resolution DAC.
3Reliability
If separate DAC modules are used for each channel to ensure independent conversion accuracy, then the conversion reliability is maintained, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent combines multiple conversion functions into a single integrated circuit with shared first MOS transistors and resistors that process digital bit signals. This merging approach maintains conversion reliability through unified signal processing while reducing manufacturing complexity and cost compared to assembling separate DAC modules for each channel.
Solution Approach 2:
Within the integrated circuit, the patent segments functions by dedicating first MOS transistors to digital bit processing and second MOS transistors to row blank signal processing. This functional segmentation within a unified structure maintains reliability by clearly defining signal paths while reducing overall manufacturing complexity through integration.
Data Source
AI summary
The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.