DAC Clock Spread-Spectrum Control for RF Image Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional RF transmitters using digital-to-analog converters (DACs) generate spurious images that can interfere with other communication systems, and existing solutions either increase the DAC sampling rate or filter order, which incur costs in terms of current and chip area.
Innovation Solution
A control unit that employs a sample rate converter and a pseudorandom binary sequence (PRBS) generator to spread the DAC clock frequency, using a frequency synthesizer to modulate the clock and pre-distort digital input data, effectively spreading the energy of DAC images across a defined frequency range while preserving the fundamental signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the DAC sampling rate is increased to reduce DAC images, then the amplitude of DAC images is reduced, but the current consumption and chip area increase
Solution Approach 1:
The patent changes the temporal distribution parameter of the DAC clock by applying spread spectrum modulation, which varies the clock frequency over time according to a pseudorandom sequence. This transforms the concentrated DAC image energy at the sampling frequency into dispersed energy across a broader frequency range, reducing peak image amplitudes without increasing the nominal sampling rate or requiring additional hardware resources
Solution Approach 2:
The patent converts the harmful concentrated DAC images into beneficial dispersed noise-like signals by spreading the energy spectrum. The pseudorandom modulation transforms the deterministic periodic images into stochastic-looking spectral distributions that occupy less harmful frequency regions and can be more easily filtered or tolerated by adjacent channels
2Object-generated harmful factors
If the DAC sampling rate is increased to reduce DAC images, then the amplitude of DAC images is reduced, but the current consumption increases
Solution Approach 1:
The patent modifies the clock frequency parameter dynamically through spread spectrum modulation rather than statically increasing the sampling rate. This allows the nominal sampling rate to remain unchanged, avoiding the proportional increase in current consumption that would result from running the DAC at higher speeds, while still achieving image reduction through spectral dispersion
Solution Approach 2:
The patent introduces dynamic frequency variation to the DAC clock using pseudorandom modulation sequences. Instead of a fixed high sampling rate that continuously consumes high current, the system uses a modulated clock that dynamically adjusts frequency moments, achieving image suppression without the sustained high power consumption of a permanently increased sampling rate
3Object-generated harmful factors
If the filter order is increased to reduce DAC images, then the amplitude of DAC images is reduced, but the device complexity increases
Solution Approach 1:
The patent applies spread spectrum modulation to the DAC clock before the signal enters the reconstruction filter stage. By pre-dispersing the DAC image energy across a broader frequency spectrum, the subsequent filter only needs to perform simple attenuation of already-reduced image components, rather than requiring high-order complex filtering to achieve the same image suppression level
Solution Approach 2:
The patent transforms the challenging task of filtering strong periodic DAC images into a simpler task of attenuating already-weakened dispersed signals. The spread spectrum technique converts the harmful concentrated images into beneficial low-level distributed noise, which requires much simpler filtering to achieve compliance with spectral masks
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
Control unit (100) for a transmission system, comprising: - a sample rate converter (10), which is coupled to a digital-to-analog converting unit (200), wherein digital input data (data_in) are feedable to the sample rate converter (10); - a PRBS generator (20), wherein an output signal (ss_div) of the PRBS generator (20) is feedable to the sample rate converter (10) and to a delay element (30), wherein an output signal (ss_div_del) of the delay element (30) is feedable to a frequency synthesizer (40), wherein the frequency synthesizer (40) is clockable by a reference clock (clk_ref) and wherein an output signal (clk_ss) of the frequency synthesizer (40) is feedable to a clock input (10a) of the sample rate converter (10) and to a clock input (200a) of the digital-to-analog converting unit (200).