DAC Clock Multiplexing for High-Frequency Analog Signal Output
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Solution Overview
Problem
Existing digital-to-analogue converters face limitations in generating analogue signals with high output frequencies beyond the sampling frequency while maintaining performance and dynamic range, often requiring additional components that increase noise, distortion, and consumption, and are not easily reconfigurable.
Innovation Solution
A device comprising a digital-to-analogue converter with a digital register and multiplexer circuits that generate and process clock signals to produce analogue signals with a spectral response centered around a frequency multiple of the sampling frequency, optimizing output power and bit rate by using multiple clock signals to increase signal frequency without additional active elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multiplier is placed at the output of the converter to translate the frequency to fm > fs/2, then the signal frequency can be increased with dynamic range equivalent to the first Nyquist zone, but additional active elements (radiofrequency source) are required which increases noise, distortion and consumption
Solution Approach 1:
The system uses the existing sampling clock signal at frequency fs to perform frequency translation, eliminating the need for separate radiofrequency sources. The sampling clock itself serves the dual purpose of digitizing the input signal and translating the output spectrum to higher frequencies through the return-to-zero operation.
Solution Approach 2:
The sampling clock signal is made multi-functional by using it both for the standard digital-to-analogue conversion process and for frequency translation of the output signal. This single clock signal performs multiple functions, eliminating the need for additional dedicated frequency translation components.
2Speed
If the sampling frequency fs is increased to generate signals beyond 2fs, then the dynamic range in the first and second Nyquist zones is increased, but converter cores have to be interleaved which produces additional parasitic signals and degrades performance
Solution Approach 1:
Instead of changing the sampling frequency to access higher frequency ranges, the invention changes the temporal structure of the output signal by applying return-to-zero operations. This parameter change in the signal waveform allows frequency multiplication without requiring higher sampling rates, thus avoiding the need for interleaved converter cores and associated parasitic signals.
3Speed
If multiple returns-to-zero operations are performed on the analogue output signal, then the signal can be generated around N×fs with low attenuation, but the returns-to-zero intervals become shorter and shorter with the increase in N, requiring rapid clock signals
Solution Approach 1:
The system uses the existing sampling clock signal to control the return-to-zero operations, eliminating the need for separate rapid clock signals. The sampling clock itself provides the timing control for the frequency multiplication process, simplifying the device architecture and reducing complexity.
Data Source
AI summary
Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.