Dynamic DAC Clock Rate Adjustment for Noise and Distortion Trade-offs
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Solution Overview
Problem
Digital-to-analogue conversion circuits, particularly switched-capacitor DACs, face challenges in achieving high noise performance due to capacitor mismatch errors and thermal noise, which become impractical to manage at higher resolutions, and existing noise reduction techniques are limited by the settling characteristics of DAC elements.
Innovation Solution
A digital-to-analogue conversion circuit that dynamically adjusts the DAC clock rate based on the amplitude of the audio signal, using a clock controller to vary the clock rate to optimize noise characteristics, reducing thermal noise at low amplitudes while avoiding distortion at high amplitudes, and incorporating a dynamic error matching module to average out capacitor mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the DAC clock rate is increased to reduce thermal noise at low signal amplitudes, then noise performance is improved, but distortion performance deteriorates at high signal amplitudes due to insufficient settling time
Solution Approach 1:
The patent implements dynamic clock rate adjustment where the DAC clock rate varies based on signal amplitude. At low signal amplitudes, a higher clock rate is used to reduce thermal noise, while at high signal amplitudes, a lower clock rate is used to ensure adequate settling time and maintain distortion performance. This dynamic adaptation resolves the contradiction by allowing the system to optimize for noise reduction when needed while preserving accuracy when signal levels require it.
Solution Approach 2:
The patent changes the operational parameter (clock rate) of the DAC based on signal conditions. By adjusting the clock rate parameter dynamically according to signal amplitude, the system can achieve low thermal noise at low amplitudes while maintaining proper settling and distortion performance at high amplitudes, thus resolving the technical contradiction between noise reduction and accuracy maintenance.
2Object-affected harmful factors
If a high-resolution DAC (15-20 bits) is used to achieve 90-120 dB signal-to-noise ratio, then noise performance is improved, but device complexity increases due to the need for accurate capacitor matching
Solution Approach 1:
The patent employs dynamic error matching where the capacitor array is dynamically switched and reordered based on signal amplitude. This dynamic approach allows the use of a simpler capacitor array with fewer elements while achieving high effective resolution through dynamic switching and error correction techniques, thus reducing device complexity while maintaining noise performance.
Solution Approach 2:
The patent changes the operational parameters of the capacitor array including switching sequences, selection patterns, and weighting factors based on signal conditions. By dynamically adjusting these parameters, the system achieves high-resolution conversion with a simpler physical capacitor array, reducing manufacturing complexity while maintaining the required 90-120 dB signal-to-noise ratio.
3Device complexity
If the DAC clock rate is reduced to simplify circuit design and reduce power consumption, then device complexity is reduced, but thermal noise increases at low signal amplitudes
Solution Approach 1:
The patent implements dynamic clock rate adjustment that allows the circuit to operate at higher clock rates when low signal amplitudes are detected (reducing thermal noise) and at lower clock rates when high signal amplitudes are present (maintaining settling performance). This dynamic adaptation enables the use of a simpler circuit design while maintaining low thermal noise through conditional high-speed operation.
Solution Approach 2:
The patent dynamically changes the clock rate parameter based on signal amplitude detection. By adjusting this parameter in real-time, the system achieves low thermal noise at low amplitudes without requiring a permanently high-clock-rate complex circuit design, thus maintaining circuit simplicity while reducing noise when needed.
4Manufacturing precision
If dynamic error matching is implemented to average out capacitor mismatches, then manufacturing precision is improved, but device complexity increases due to additional switching control circuitry
Solution Approach 1:
The patent implements dynamic error matching with amplitude-dependent switching sequences. The complexity of the error matching circuitry is dynamically adapted based on signal amplitude - using more aggressive error correction at low amplitudes where noise is more critical, and simpler correction at high amplitudes. This dynamic approach improves effective capacitor matching accuracy while minimizing the operational complexity of the control circuitry.
Solution Approach 2:
The patent dynamically changes the error matching parameters including switching sequences, selection patterns, and correction weights based on signal conditions. By adjusting these parameters dynamically, the system achieves high capacitor matching accuracy without requiring permanently complex control circuitry, as the full error matching capability is only activated when needed at low signal amplitudes.
Data Source
AI summary
This application relates to digital-to-analogue conversion with improved noise performance. Embodiments relate to digital-to-analogue conversion circuits (300) for converting a digital audio signal to an analogue audio signal having a digital-to-analogue converter (104) operable at a plurality of DAC clock rates. A first clock controller (301-1) controls the DAC clock rate based on an indication of the amplitude of the audio signal. The DAC clock rate (CK1) may be increased for low amplitude signal, where noise is important, to reduce the in-band thermal noise of the DAC. At higher amplitudes, when noise is less audible, the DAC clock rate may be reduced to avoid distortion. The amplitude of the audio signal may be monitored by a digital level detector (302) or in some cases by an analogue level detector (303). The DAC may be an oversampling DAC with an input interpolator (101) The conversion circuit may also include a word-length reduction module (102) and a dynamic error matching module (103) whose clock rates may also be varied based on the signal.