DAC Current Generation Using Calibrated Current Mirrors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital-to-analogue converter (DAC) circuitry faces challenges in achieving accurate and efficient current generation, particularly in segmented architectures where scaling down currents for least significant bits (LSBs) is difficult without compromising accuracy or requiring large numbers of segments, and impedance ladder accuracy becomes a concern at small current levels.
Innovation Solution
The implementation of current-generation circuitry that includes candidate current sources, comparator circuitry, and control circuitry to calibrate and adjust currents, using current mirrors to maintain accurate ratios and avoid the need for scaling down currents, thereby enabling precise and efficient current generation across all bits in DACs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If segmented architecture is applied to all bits of DAC, then resolution and accuracy are improved, but the number of segments and device complexity increase significantly
Solution Approach 1:
The patent applies segmentation to the most significant bits (MSBs) of the DAC, dividing them into multiple segments (e.g., 6 segments for 6 MSBs). This allows high-resolution conversion for the upper bits while avoiding the complexity of segmenting all bits. The segmented architecture handles the MSBs with dedicated current sources and switching circuits, while the least significant bits (LSBs) use a non-segmented approach, thus resolving the contradiction between resolution and complexity.
Solution Approach 2:
The patent implements different architectural approaches for different parts of the DAC: segmented architecture for MSBs where high precision is critical, and non-segmented architecture for LSBs where the current contribution is naturally smaller. This local differentiation allows each part to be optimized independently, achieving high overall accuracy without requiring all bits to be segmented.
2Device complexity
If non-segmented architecture is used for LSBs, then device complexity is reduced, but current scaling accuracy becomes difficult to achieve
Solution Approach 1:
The patent introduces an impedance ladder network as an intermediary element that connects the segmented MSB section to the non-segmented LSB section. This impedance ladder provides precise current scaling ratios (e.g., 1:2, 1:4, 1:8) between the different bit sections without requiring complex scaling circuits in each LSB path. The intermediary structure ensures accurate current weighting for LSBs while maintaining circuit simplicity.
3Measurement precision
If current scaling is applied for LSBs, then resolution is maintained, but impedance ladder accuracy becomes a concern at small current levels
Solution Approach 1:
The patent replaces the traditional resistive impedance ladder with a current mirror-based scaling mechanism. Instead of relying on precise resistor ratios that become problematic at small current levels, the invention uses current mirrors to replicate and scale currents with high accuracy. The current mirrors maintain precise current ratios through transistor matching, providing reliable scaling even at the small current levels associated with LSBs.
4Adaptability or versatility
If LSB currents are scaled down significantly, then DAC range is covered, but accuracy and speed of current generation deteriorate
Solution Approach 1:
The patent performs preliminary current generation at higher current levels in the segmented MSB section, where speed is less critical but accuracy is paramount. The scaled-down currents for LSBs are then derived from these pre-generated currents through the impedance ladder and current mirrors. This preliminary action allows the system to maintain high speed for the dominant MSB contributions while achieving accurate scaling for the smaller LSB currents.
Data Source
Figure 1~12
Figure 2
Figure 3A~3B
AI summary
Current-generation circuitry, comprising: a plurality of candidate current sources operable to generate respective candidate currents; an output current source operable to generate an output current; comparator circuitry; and control circuitry operable to control the current sources and the comparator circuitry and connections therebetween to: in an adjustment step, generate an adjustment current by selecting one of the candidate currents or by summing together a plurality of the candidate currents, and calibrate at least a plurality of the candidate current sources including each candidate current source which contributes to that adjustment current by comparing that adjustment current to a comparative current using the comparator circuitry and adjusting control signals applied to the candidate current sources being calibrated to adjust their candidate currents until that adjustment current and the comparative current are brought into a defined relationship; and in a calibration step, following the adjustment step, generate a reference current by selecting one of the candidate currents generated by the candidate current sources calibrated in the adjustment step or by summing together a plurality of the candidate currents generated by those candidate current sources, and calibrate the output current source by comparing its output current to that reference current and adjusting a control signal applied to that output current source to adjust its output current until its output current and that reference current are brought into a defined relationship.