Differential DAC Current Scaling for Low Glitch Noise
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Solution Overview
Problem
High-speed, high-resolution digital-to-analog converters (DACs) in wireless communication devices face challenges in controlling glitch noise, particularly in low-power, wideband applications, which can lead to interference with signal transmission due to delay differences across DAC stages.
Innovation Solution
A DAC design with input stages generating the same current and using resistive networks to scale currents based on binary weights, combined with an impedance attenuator to maintain impedance and voltage differences, reduces glitch noise by matching current flows through transistor switches across stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-speed, high-resolution DAC is used in wireless communication devices, then conversion speed and resolution are improved, but glitch noise increases due to delay differences between stages
Solution Approach 1:
The patent changes the parameter of current magnitude across stages by using resistive networks to scale currents in LSB stages. This parameter change ensures that current magnitudes are matched across all stages despite different bit weights, thereby reducing glitch noise while maintaining high resolution and speed performance
2Object-generated harmful factors
If current magnitudes are matched across all stages by using resistive networks, then glitch noise is reduced, but device complexity increases
Solution Approach 1:
The patent applies local quality by introducing resistive networks specifically in the LSB stages where current magnitude matching is needed, rather than uniformly across all stages. This targeted approach reduces glitch noise in critical areas while minimizing overall circuit complexity
3Object-generated harmful factors
If out-of-band noise is reduced to prevent receiver channel desensitization, then signal quality is improved, but DAC design complexity increases
Solution Approach 1:
The patent changes the current magnitude parameter in LSB stages using resistive networks to reduce out-of-band noise that causes receiver channel desensitization. This parameter modification directly addresses the noise issue while maintaining a relatively simple DAC architecture
Data Source
AI summary
An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2M−1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver their currents differentially to the DAC's current summing nodes. Each of the remaining (N−M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N−M) stages deliver their currents to the current summing nodes differentially. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.