DAC Deglitcher Using Clock Delay to Reduce Glitch Impulses
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Solution Overview
Problem
Resistor ladder DACs experience significant transient errors due to varying analog propagation delays among switches, leading to substantial glitch impulses that are difficult to filter and increase costs, power consumption, and area when addressed with sample and hold circuits.
Innovation Solution
A clock delay circuit is introduced to synchronize the update of digital input signals, compensating for propagation delays between most significant bits and lower bits, allowing for equivalent segment weighting and minimizing delay differences, thereby reducing glitch impulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a R-2R ladder network DAC is used to achieve binary weighted voltage conversion, then the circuit complexity is reduced and ease of manufacture is improved, but transient errors and glitch impulses increase due to varying propagation delays among switches
Solution Approach 1:
The patent segments the R-2R ladder network into multiple independent sections, each with its own switches and resistors. This segmentation allows each segment to be optimized for minimal propagation delay while maintaining the overall binary-weighted functionality. The segmented architecture reduces the varying delay problem by creating more uniform signal paths across different bit positions.
Solution Approach 2:
The patent employs preliminary action by pre-synchronizing the switching operations of different bit positions using a delayed clock signal. The less significant bits are switched before the more significant bits, allowing their transient responses to settle before the larger transients from significant bits occur. This timing coordination reduces the overall glitch impulse at the output.
2Object-generated harmful factors
If sample and hold circuits are added to reduce glitch impulses, then transient error reduction is improved, but device complexity, power consumption, and chip area increase
Solution Approach 1:
The patent extracts the glitch reduction function from the traditional sample and hold circuit approach and implements it directly within the DAC switching architecture. By incorporating delay elements and synchronized switching control directly in the DAC structure, the patent eliminates the need for separate external sample and hold circuits, thereby reducing overall device complexity while maintaining transient error performance.
3Manufacturing precision
If binary weighted resistor network is used for high resolution DAC, then manufacturing precision requirements increase due to large range of resistor values, but the patent uses R-2R ladder to simplify this
Solution Approach 1:
The patent applies local quality by making each segment of the R-2R ladder network have uniform resistor characteristics and switching properties. Within each segment, the resistors are designed with identical values and the switches are matched for minimal delay variation. This local uniformity reduces propagation delay differences while maintaining the binary-weighted functionality across the entire DAC structure.
Data Source
AI summary
A digital to analog converter that receives a digital signal and that converts the digital signal to an analog input signal is provided. The converter may include a group of most significant bits. The group is decoded to drive a plurality of equivalent most significant segments. The converter may also include a second group of bits. The second group is decoded to drive a second plurality of equivalent segments.