Capacitor Ladder DAC Delay Equalization for High-Frequency Linearity
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Solution Overview
Problem
Capacitor ladder digital-to-analog converters (DACs) exhibit nonlinearity issues, particularly at higher frequencies due to phase and delay differences in responses from different input terminals, leading to dynamic and frequency-dependent nonlinearity, which worsens with increasing signal and sampling frequencies.
Innovation Solution
The implementation of an input circuit with strategically connected capacitors between input terminals and signal ground, along with a capacitor ladder circuit with adjustable capacitance ratios, helps equalize delays and counteract parasitic capacitance effects, improving linearity by using capacitors with capacitance ratios other than the conventional 2:1 ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If capacitor ladder DACs are used for high frequency applications, then bandwidth capability is improved, but linearity deteriorates due to phase and delay differences
Solution Approach 1:
The patent changes the capacitance ratio parameter from the conventional 2:1 ratio to other ratios (such as 1:1 or other custom ratios) to equalize the delays from different input terminals to the output. This parameter modification allows the DAC to maintain good linearity at higher frequencies while preserving bandwidth capability.
2Device complexity
If conventional 2:1 capacitance ratio is used in capacitor ladder DAC, then device complexity is reduced, but linearity at high frequencies deteriorates
Solution Approach 1:
The patent modifies the capacitance ratio parameter from the conventional 2:1 ratio to alternative ratios such as 1:1 or other custom ratios. This parameter change enables the equalization of delays from different input terminals, improving linearity at high frequencies while maintaining reasonable device complexity.
3Productivity
If signal and sampling frequencies are increased, then data throughput is improved, but nonlinearity worsens due to frequency-dependent phase differences
Solution Approach 1:
The patent changes the capacitance ratio parameter to values other than the conventional 2:1 ratio, which equalizes the frequency-dependent phase and delay differences from different input terminals. This allows the system to operate at higher signal and sampling frequencies with improved data throughput while maintaining acceptable linearity performance.
Data Source
AI summary
A DAC (60) is disclosed. It comprises an input port comprising N input terminals p1, p2, . . . , pN configured to receive voltages representing N input bits b1, b2, . . . , bN, respectively, wherein the significance of bj is higher than for bj−1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C1, C2, . . . , CN with capacitance C, each having a first terminal and a second terminal. Capacitor Cj is connected with its first terminal to the terminal pj of the input port. For each j=1, 2, . . . , N−1, the capacitor ladder circuit (100) comprises a capacitor (150j) with capacitance xC connected between the second terminal of capacitor Cj and the second terminal of capacitor Cj+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (1601-160N), each connected between a unique one of the input terminals p1, p2, . . . , pN of the input port and signal ground.