DAC Delta-Sigma Calibration for Amplitude and Timing Errors
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Solution Overview
Problem
Digital-to-analog converters (DACs) suffer from imperfections such as amplitude and timing errors, which degrade their performance and dynamic range, and existing calibration methods like using square waves are limited in scalability and practicality, especially for high-resolution applications.
Innovation Solution
The use of delta-sigma patterns to drive reference and test DAC cells, allowing for the calibration of amplitude and timing errors by generating coded test signals that cancel out at the analog output, leaving a residual signal representative of the errors, which can be sensed and corrected using a sensing circuit and control circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional square wave calibration methods are used, then the calibration process is simple to implement, but the method is limited in scalability and cannot effectively calibrate high-resolution DACs
Solution Approach 1:
The patent changes the calibration signal from traditional square waves to delta-sigma modulated sequences with varying parameters (oversampling ratio, modulation depth, frequency). This allows the calibration method to adapt to different resolution requirements and DAC configurations, resolving the contradiction between implementation simplicity and scalability to high-resolution applications.
Solution Approach 2:
The calibration system dynamically adjusts the delta-sigma modulator parameters during calibration based on the specific DAC being tested. The system can adaptively change oversampling ratios, modulation frequencies, and sequence lengths to optimize calibration effectiveness for different resolution levels, enabling scalability from low to high-resolution DACs while maintaining ease of use.
2Measurement precision
If additional DAC cells are added to improve calibration accuracy, then the calibration precision improves, but the device area and complexity increase
Solution Approach 1:
The patent uses delta-sigma modulated test signals that create virtual calibration patterns without requiring physical additional DAC cells. The modulated sequences effectively copy and amplify the error signals through digital processing, achieving high calibration precision using the existing DAC hardware resources, thus avoiding area increase.
Solution Approach 2:
The patent moves the calibration enhancement from the spatial domain (adding more physical DAC cells) to the temporal and signal processing domain (using delta-sigma modulated sequences with high oversampling ratios). This dimensional shift allows achieving higher calibration accuracy without increasing device area, as the precision improvement comes from signal processing rather than hardware multiplication.
3Manufacturing precision
If the DAC cell size is increased to reduce timing errors, then the timing precision improves, but the device area and manufacturing cost increase
Solution Approach 1:
The patent replaces the mechanical approach of increasing physical DAC cell size to reduce timing errors with a signal processing approach using delta-sigma modulation. The timing error calibration is achieved through digital signal processing of modulated test sequences, substituting physical enlargement with intelligent signal analysis, thus maintaining compact cell sizes while improving timing precision.
Solution Approach 2:
The patent introduces delta-sigma modulated test signals as an intermediary between the DAC output and the error measurement process. These modulated signals act as a mediator that amplifies and highlights timing errors, allowing precise measurement and calibration without needing larger physical cells. The intermediary signal processing enables high precision with small physical dimensions.
Data Source
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AI summary
A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as "non-idealities") result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.