Digital Correction of Multibit DAC Nonlinearity
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Solution Overview
Problem
Existing multi-bit digital-to-analog converters (DACs) face challenges in achieving high resolution due to integral nonlinearity errors, which are difficult to correct at low oversampling ratios without increasing circuit complexity and power consumption.
Innovation Solution
A digital correction method using a low-resolution calibration analog-to-digital converter (CADC) to estimate and store nonlinearity errors in a RAM table, combined with data-weighted averaging (DWA) for mismatch shaping, allowing for compensation of ADAC distortion in the digital domain without additional digital filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If digital correction methods are used to achieve high resolution in multi-bit DACs, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before the DAC enters normal operation. A calibration ADC measures the actual output values of the DAC during a calibration phase, and these measurements are stored in a lookup table. During normal operation, the pre-computed correction values from the lookup table are applied to compensate for nonlinearity errors, avoiding the need for complex real-time correction circuits.
Solution Approach 2:
The patent uses copying by creating a digital replica of the DAC's nonlinearity characteristics through calibration measurements. The calibration ADC captures the actual transfer function of the DAC, and this information is stored as correction values in a lookup table. This digital copy of the error characteristics is then used to correct the DAC output without requiring additional analog correction circuitry.
2Manufacturing precision
If digital correction methods are used to achieve high resolution in multi-bit DACs, then manufacturing precision is improved, but power consumption increases
Solution Approach 1:
The calibration process is performed once during initialization or manufacturing, and the correction values are stored in a lookup table. During normal operation, only simple table lookup and addition operations are required, which consume minimal power compared to continuous complex correction computations or high-precision analog circuits operating continuously.
Solution Approach 2:
The patent uses a low-resolution calibration ADC that is simpler and consumes less power than a high-resolution ADC would require. The calibration ADC is used only during the calibration phase, and its lower resolution is sufficient for capturing the nonlinearity errors. This disposable-like approach uses a simpler component for the calibration task rather than deploying a complex high-precision component continuously.
3Measurement precision
If high oversampling ratios are used to improve DAC performance, then measurement precision is improved, but productivity decreases
Solution Approach 1:
This analogy doesn't directly apply to the digital correction method. The patent achieves high accuracy without relying on high oversampling ratios by using digital correction through calibration and lookup tables, effectively replacing the need for excessive sampling with a more efficient correction approach.
Data Source
AI summary
Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.