DAC Transmit Driver Slices for Higher Bandwidth, Lower PAD Loading
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Solution Overview
Problem
High-speed serial communication links face challenges in maintaining bandwidth without increasing PAD loading, leading to inter-symbol-interference and degradation of bit error rate due to insufficient frontend bandwidth in DAC-based transmit drivers.
Innovation Solution
A DAC-based transmit driver architecture with multiple DAC slices, each having a single bias transistor coupled between the output of a multiplexing stage and the output node, along with an optional active inductor to improve bandwidth and reduce common-mode ripple, thereby decreasing PAD loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple bias transistors are used in each DAC slice, then bandwidth is improved, but PAD loading increases
Solution Approach 1:
Multiple bias transistors in each DAC slice are merged into a single bias transistor that is shared across all DAC slices. This consolidation maintains the necessary biasing function while reducing the total number of transistors connected to the PAD, thereby decreasing PAD loading while preserving bandwidth performance.
Solution Approach 2:
The single bias transistor is designed to serve multiple DAC slices simultaneously, performing a universal biasing function. This multi-functional approach allows the same transistor to support multiple current paths without requiring separate dedicated transistors for each slice, thus reducing overall PAD loading.
2Extent of automation
If DAC-based transmit driver architecture is used, then serialization capability is achieved, but frontend bandwidth becomes insufficient
Solution Approach 1:
The transmit driver is divided into multiple independent DAC slices, each capable of contributing to the overall serialization function. This segmentation allows parallel current paths to be established, increasing the aggregate frontend bandwidth while maintaining the serialization capability through coordinated operation of the slices.
Solution Approach 2:
The architecture transitions from a single-path DAC structure to a multi-path parallel structure, adding a dimensional aspect to the current flow. By creating multiple parallel current paths through separate DAC slices, the system achieves both serialization capability and enhanced frontend bandwidth simultaneously.
3Reliability
If frontend bandwidth is increased, then inter-symbol-interference is reduced, but device complexity increases
Solution Approach 1:
The frontend is segmented into multiple parallel DAC slice paths, each contributing to the overall bandwidth. This segmentation approach increases frontend bandwidth to reduce inter-symbol-interference while keeping each individual slice relatively simple, thereby managing overall device complexity through modular repetition rather than monolithic complexity.
Data Source
AI summary
A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.