DAC Transmit Driver Impedance Tuning for Glitch Reduction
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Solution Overview
Problem
High-speed serial communication links face challenges in impedance matching and transition glitches due to process variations and voltage gaps, leading to reduced link performance and increased noise in SerDes systems.
Innovation Solution
A DAC-based transmit driver architecture with tunable impedance control and a predriver circuit having two inverter paths with different transistor strengths, allowing for impedance adjustment and reduced output voltage spikes during data transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional transmit driver architecture is used, then the circuit structure is simple, but the impedance matching is poor and transition glitches occur
Solution Approach 1:
The transmit driver is divided into multiple independent DAC driver slices, each handling a portion of the impedance control. This segmentation allows precise adjustment of output impedance by selectively enabling/disabling slices, improving impedance matching without requiring a completely complex redesign of the entire driver circuit.
Solution Approach 2:
The patent implements dynamic impedance control by making the output impedance tunable through the impedance control circuit. The impedance can be adjusted in real-time based on operating conditions, allowing the driver to maintain optimal matching across different signal levels and frequencies, thereby improving reliability without fixed complex structure.
2Use of energy by moving object
If the output impedance is made smaller than load impedance to increase voltage swing, then the voltage swing exceeds supply voltage, but this causes greater sensitivity to impedance mismatch and transition glitches
Solution Approach 1:
The patent changes the output impedance parameter dynamically to be smaller than the load impedance, enabling voltage swing to exceed the supply voltage. This parameter change is controlled through the impedance control circuit that adjusts the effective output impedance based on operating conditions, allowing high voltage swing while managing the associated noise and glitch sensitivity through coordinated control.
Solution Approach 2:
The impedance control circuit implements feedback mechanisms to monitor and adjust the output impedance in response to operating conditions. This feedback ensures that when voltage swing exceeds supply voltage, the system can compensate for potential instability and reduce transition glitches by adapting the impedance to maintain optimal performance.
3Adaptability or versatility
If DAC driver slices are used for impedance control, then the impedance can be tuned to match load, but the circuit complexity increases
Solution Approach 1:
Each DAC driver slice is designed to serve multiple functions: it contributes to the differential output signal generation and simultaneously provides impedance control capability. This multi-functionality reduces the need for separate dedicated impedance control circuits, allowing the system to achieve tunable impedance matching without proportionally increasing overall circuit complexity.
Data Source
AI summary
A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.