Voltage-Mode DAC Driver With Parallel Impedance Tuning
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) face challenges in accurately and efficiently tuning output impedance, particularly in maintaining a consistent 50 ohms aggregate impedance, which can be affected by sample-to-sample variations and introduce additional capacitance at higher frequencies.
Innovation Solution
A voltage-mode DAC architecture that includes an array of output impedance units disposed in parallel, allowing for selective activation of a variable number of units to achieve a desired aggregate output impedance, with optional auxiliary bit slices and adaptive tuning capabilities to fine-tune the impedance and scale the input codeword, ensuring high-accuracy and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple separately selectable impedance units are configured in series for post-silicon tuning, then output impedance accuracy is improved, but additional capacitance is introduced to the output node which alters termination impedance at higher frequencies
Solution Approach 1:
The output impedance unit is divided into multiple separately selectable impedance units (e.g., 14 kohms and multiple 1 kohms units) that can be independently switched. This segmentation allows precise tuning of the aggregate output impedance by selectively activating specific units to compensate for sample-to-sample variations and achieve the desired 50 ohms termination.
Solution Approach 2:
The impedance units are made dynamically selectable through switch circuitry that responds to tuning signals. This dynamic configuration allows the system to adapt the output impedance after fabrication by selectively activating or deactivating specific impedance units based on measured performance, enabling post-silicon calibration without redesign.
2Productivity
If multiple DAC drivers are employed to process each bit of the input word, then processing capability is improved, but sample-to-sample variations cause actual resistance of each output impedance unit to vary
Solution Approach 1:
A feedback mechanism is implemented where the actual output impedance is measured and compared against the target value (50 ohms). Based on this feedback, control circuitry selectively activates specific impedance units in each DAC driver to compensate for variations, ensuring that the aggregate output impedance meets specifications despite manufacturing tolerances in individual components.
Solution Approach 2:
The system changes the effective resistance parameter by selectively activating different impedance units within each DAC driver. By adjusting which units are active, the actual resistance values are tuned to compensate for sample-to-sample variations, maintaining consistent aggregate output impedance across multiple drivers while preserving full processing capability.
3Measurement precision
If auxiliary bit slices are added for impedance tuning, then impedance tuning accuracy is improved, but device complexity increases
Solution Approach 1:
The auxiliary bit slices are designed to perform multiple functions: they can be used for impedance tuning by selectively activating their impedance units, and they can also process additional data bits to increase DAC resolution. This multi-functionality allows the same hardware resources to serve both impedance calibration and signal processing purposes, reducing overall device complexity while maintaining high tuning accuracy.
Solution Approach 2:
Instead of designing completely separate dedicated tuning circuitry, the system uses partial activation of existing bit slice resources. The auxiliary bit slices are not always fully active for data processing but can be partially utilized for impedance tuning when needed, optimizing the balance between tuning accuracy and device complexity by using resources only to the extent necessary.
Data Source
AI summary
A voltage-mode digital-to-analog converter (DAC) includes input circuitry and an array of output impedance units disposed in parallel. The input circuitry receives a digital word of N bits. A selectable number of the output impedance units are activated to produce a desired aggregate output impedance. The selectable number is free to be a number different than N.