DAC Calibration Circuit With Dual Offset Compensation Loops
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Solution Overview
Problem
Digital-to-analog converters (DACs) in RF systems face precision issues due to errors caused by direct current (DC) and chopper offsets, which affect calibration accuracy and signal processing.
Innovation Solution
The implementation of a calibration circuit with bias control, driver, and current steering circuits in each DAC cell allows for individual calibration to adjust timing and amplitude errors, reducing offset impacts through compensation loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single offset compensation loop is used in DAC calibration, then the device complexity is reduced, but the measurement precision and calibration accuracy deteriorate due to inability to separately compensate DC and chopper offsets
Solution Approach 1:
The calibration circuit is segmented into two independent offset compensation loops: a first loop for DC offset compensation and a second loop for chopper offset compensation. Each loop independently measures and compensates its specific offset type, preventing mutual interference and enabling precise separate compensation of both offsets, thereby resolving the contradiction between circuit simplicity and calibration accuracy.
Solution Approach 2:
Dummy DAC cells are introduced as intermediary elements to facilitate separate offset measurements. The first dummy DAC cell is used exclusively for DC offset measurement while the second dummy DAC cell is used for chopper offset measurement, enabling the calibration circuit to independently characterize and compensate each offset type without cross-contamination.
2Device complexity
If offset compensation is performed without separate loops, then the device complexity is reduced, but the reliability of signal processing deteriorates due to offset-induced errors
Solution Approach 1:
The calibration system is divided into two independent compensation loops that operate separately to measure and correct DC and chopper offsets. This segmentation ensures that each offset type is compensated with dedicated circuitry, eliminating measurement interference and improving the reliability of signal processing by ensuring accurate offset removal.
Solution Approach 2:
Both offset compensation loops implement feedback mechanisms where the measured offsets are fed back to adjust the DAC cell outputs. The first loop feeds back DC offset measurements and the second loop feeds back chopper offset measurements, enabling continuous correction and improving signal processing reliability through active compensation.
3Manufacturing precision
If individual calibration of each DAC cell is implemented, then the manufacturing precision is improved, but the device complexity increases due to additional bias control and current steering circuits
Solution Approach 1:
Each DAC cell is equipped with dedicated bias control circuits and current steering circuits that enable individual calibration. The segmentation of control functions into separate circuits for each cell allows precise independent adjustment of timing and amplitude parameters, achieving high manufacturing precision while organizing complexity in a modular and manageable manner.
Solution Approach 2:
The calibration circuitry is distributed locally to each DAC cell rather than using a centralized approach. Each cell has its own bias control and current steering circuits that can be independently adjusted, allowing local optimization of calibration accuracy for each cell while maintaining overall system functionality.
Data Source
AI summary
Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.