Current-Steering DAC Calibration for Dynamic Mismatch Accumulation
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Solution Overview
Problem
Current-steering DACs suffer from random and systematic time-delay mismatches between DAC unit cells, leading to dynamic nonlinearity and harmonic distortion, which degrade performance by reducing the signal-to-noise-and-distortion ratio (SNDR).
Innovation Solution
A method involving a capacitive element to accumulate current mismatches between DAC cells and a reference cell, with polarity switching to cancel static mismatches and integrate dynamic mismatches, allowing for the determination of relative time delays and reordering of DAC cells to reduce dynamic nonlinearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current-steering DACs use multiple DAC unit cells, then the DAC can provide higher resolution and broader frequency response, but time-delay mismatches between cells cause dynamic nonlinearity and harmonic distortion that degrade SNDR
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before actual DAC operation to determine time-delay values for each unit cell. The system pre-characterizes each cell's timing characteristics and stores these values for use during normal operation, allowing the main DAC to compensate for delays without real-time measurement overhead.
Solution Approach 2:
The patent implements feedback by using the measured time-delay values to adjust the operation of DAC unit cells. The calibration system measures actual delay characteristics and feeds this information back to control the timing of each cell, enabling dynamic compensation that maintains SNDR performance across varying operating conditions.
2Measurement precision
If calibration measurements are performed for each DAC unit cell, then accurate time-delay values can be determined, but the calibration process becomes time-consuming and complex
Solution Approach 1:
The patent merges multiple calibration measurements into a single integrated process. Rather than separately measuring offset delays and dynamic delays for each cell, the system performs both measurements simultaneously using the same test architecture and signal sequences, reducing total calibration time while maintaining measurement precision.
Solution Approach 2:
The patent discards static offset delay information and recovers only the dynamic time-delay characteristics that affect SNDR performance. By filtering out the static component through differential measurement techniques, the system focuses calibration efforts on the dynamic parameters that actually impact performance, reducing measurement complexity.
3Reliability
If static current mismatch is accumulated during calibration, then it masks the dynamic current mismatch information, but ignoring static mismatch simplifies the calibration process
Solution Approach 1:
The patent applies preliminary anti-action by introducing a reverse polarity phase in the calibration sequence. The system first accumulates mismatch information with one polarity, then accumulates with reversed polarity, allowing static offset components to cancel out before the final measurement is taken. This pre-compensation approach eliminates masking effects without requiring complex subtraction operations.
Solution Approach 2:
The patent uses periodic action by implementing a cyclic calibration sequence that alternates between different accumulation phases. The calibration process periodically switches between accumulating with normal polarity and reversed polarity, enabling dynamic mismatch information to be extracted through the periodic variation while static components average out over complete cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances DAC performance by reducing dynamic nonlinearity and improving SNDR by accurately determining and compensating for time delays between DAC cells.
Implementation Method 1
a capacitive element; an integrator comprising a first input coupled to a first terminal of the capacitive element and a second input coupled to a second terminal of the capacitive element
Data Source
AI summary
Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.