Capacitive DAC Electrode Layout for Smaller Electro-Optical Circuits
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Solution Overview
Problem
Existing DA conversion circuits for electro-optical devices require a wide space for capacitance elements, particularly due to the need for multiple basic capacitance elements coupled in parallel, which increases the space required for the capacitance element unit.
Innovation Solution
A DA conversion circuit with a capacitance element unit that includes a first capacitance element corresponding to a first bit, a second capacitance element with a greater weight, and a third and fourth capacitance element, electrically coupled in parallel, where the overlap areas of the electrodes are optimized to reduce the space required, allowing for a more compact configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple basic capacitance elements are arranged in parallel with weighting corresponding to power of 2, then the DA conversion function is achieved, but the space required for the capacitance elements increases significantly
Solution Approach 1:
The capacitance element unit is divided into multiple individual capacitance elements (first, second, third, and fourth capacitance elements), each corresponding to different bit positions. This segmentation allows independent optimization of each element's area while maintaining the overall weighted sum function for DA conversion precision.
Solution Approach 2:
Different capacitance elements are assigned different overlap areas between electrodes based on their bit weight significance. The first capacitance element has a smaller overlap area (less than half of the second), while the third and fourth elements have areas substantially the same as the second. This local quality differentiation optimizes the total area while preserving the required precision for each bit position.
2Stability of the object's composition
If capacitance elements are arranged with standard overlap areas for each bit, then the DA conversion linearity is maintained, but the overall circuit size increases
Solution Approach 1:
The overlap area parameter of the capacitance elements is changed and optimized based on bit weight. Instead of using uniform or proportionally scaled areas, the first capacitance element uses an area less than half of the second, while the third and fourth elements match the second's area. This parameter optimization maintains the weighted sum relationship required for linearity while reducing total area.
Data Source
AI summary
A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.