Dynamic Element Matching in Multi-Bit DACs for Better Linearity
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Solution Overview
Problem
Multi-bit digital-to-analog converters (DACs) driven by thermometer decoders suffer from non-linearities due to device mismatches and layout parasitics, leading to severe linearity degradations in the conversion process, with existing calibration methods being complex, costly, and inconvenient.
Innovation Solution
A dynamic element matching system that uses a plurality of sequential register groups, decode circuitry, and pointer control circuitry to pseudo-randomly enable or disable registers based on a digital input signal, derivative, shuffle, and spread spectrum control techniques to distribute DAC element utilization and transition rates, effectively turning mismatch-induced distortion into white noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermometer decoder is used in multi-bit DAC, then monotonous performance is improved, but linearity is degraded due to device mismatches and layout parasitics
Solution Approach 1:
The patent applies dynamic element matching by making the DAC element selection dynamic rather than static. The thermometer decoder dynamically selects which DAC elements to activate based on pseudo-random sequences that rotate through different element combinations, preventing any single mismatched element from consistently degrading linearity while maintaining monotonic performance.
Solution Approach 2:
The patent changes the operational parameters of the DAC by varying the activation pattern of DAC elements over time using pseudo-random sequences. By changing which elements are activated in each time period and rotating through different patterns, the system transforms deterministic mismatch errors into randomized noise, improving effective linearity while preserving monotonicity.
2Manufacturing precision
If calibration is applied to address mismatch errors, then linearity is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements a self-calibrating approach where the system automatically compensates for mismatch errors through dynamic element matching without requiring external calibration equipment or complex calibration algorithms. The pseudo-random rotation of element selections inherently averages out mismatch errors, providing continuous self-correction of linearity issues.
Solution Approach 2:
The patent replaces expensive and complex calibration hardware with simple, low-cost pseudo-random sequence generators and rotators that can be implemented in standard digital logic. This substitution dramatically reduces the cost and complexity of error correction while maintaining effective linearity improvement.
3Manufacturing precision
If dynamic element matching is implemented, then linearity is improved at low cost, but additional circuitry is required
Solution Approach 1:
The patent designs the pseudo-random sequence generator and element rotation logic to serve multiple functions: they not only improve linearity through dynamic matching but also distribute switching activity evenly across all DAC elements, reducing hot-spot heating and improving power efficiency. This multi-functionality justifies the added circuitry by delivering multiple performance benefits simultaneously.
Data Source
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AI summary
A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.