DAC Unit Cell Fill Order for Linearity and Phase Balance
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Solution Overview
Problem
The physical and logical layout of unit cells in digital-to-analog converters (DACs) affects the speed and linearity of the DACs, leading to phase delays and synchronicity issues, and variations in analog output due to uneven activation of unit cells.
Innovation Solution
Implementing a fractal DAC with dynamic and static alternating fill order (AFO) logic to homogenize data path lengths and alternate unit cell activations, using decision units to decode digital signals and control unit cell operations, thereby reducing nonlinearity and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If unit cells are activated in conventional order based on physical layout, then the DAC structure is simple, but phase delays and synchronicity issues occur due to varying data path lengths
Solution Approach 1:
The patent implements dynamic alternating fill order (AFO) logic that changes the activation sequence of unit cells based on the current digital signal value. Instead of a fixed activation order, the system dynamically alternates between different fill patterns (e.g., filling from left to right, then right to left, then alternating by rows), which adapts to minimize path length variations and reduce phase delays across different signal conditions.
Solution Approach 2:
The unit cell array is divided into multiple segments or groups that can be activated in alternating sequences. The AFO logic segments the activation process into alternating phases where different groups of unit cells are activated in different orders, effectively breaking up the long data paths into shorter segments and reducing overall phase delay.
2Manufacturing precision
If unit cells are activated in conventional order, then the control logic is simple, but linearity deteriorates due to uneven activation patterns
Solution Approach 1:
The dynamic AFO logic continuously adjusts the activation pattern based on the digital input signal. By alternating the fill direction and sequence dynamically, the system ensures more uniform activation across the unit cell array, which improves linearity by reducing the unevenness that occurs with conventional static activation orders.
Solution Approach 2:
The AFO logic implements periodic alternation between different fill patterns. The activation sequence periodically switches between left-to-right, right-to-left, and row-by-row alternating patterns, creating a regular periodic structure in the activation that averages out linearity errors and improves overall precision.
3Object-affected harmful factors
If conventional data path layout is used, then the physical layout is simple, but noise increases due to varying path lengths and activation patterns
Solution Approach 1:
The patent introduces asymmetric activation patterns through the AFO logic, where unit cells are activated in alternating asymmetric sequences rather than uniform symmetric orders. This asymmetric activation distributes the switching noise more evenly across the frequency spectrum and reduces correlated noise that would occur with conventional symmetric activation patterns.
Solution Approach 2:
The dynamic nature of the AFO logic creates time-varying activation patterns that modulate the noise characteristics. By continuously changing the activation sequence, the system spreads noise energy over time and frequency, reducing peak noise levels and improving the signal-to-noise ratio.
Data Source
AI summary
A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.