DAC Force-Sense Switch Architecture for Low-INL Linearity
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Solution Overview
Problem
Conventional voltage-mode digital-to-analog converters (DACs) face challenges with high integral non-linearity (INL) errors due to the resistance and leakage currents of CMOS switches, particularly at higher voltages, which necessitate the use of large switches that increase silicon area, parasitic capacitance, and leakage current, making miniaturization difficult and costly.
Innovation Solution
The implementation of a digital-to-analog converter with a pair of operational amplifiers and switch-controlled cells, each containing a resistor and two pairs of force/sense switches, where the force switches provide conductive paths and sense switches create feedback loops to overcome voltage losses, improving linearity and reducing the need for large switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If large CMOS switches are used to reduce switch resistance and INL error, then linearity improves, but silicon area increases and leakage current increases
Solution Approach 1:
The patent divides the switching function into two separate switch pairs per cell: force switches and sense switches. This segmentation allows each switch to be optimized for its specific function, enabling the use of smaller switches overall while maintaining linearity performance. The force switches handle current flow while sense switches monitor voltage, separating the heavy current path from the measurement path.
Solution Approach 2:
The patent introduces sense switches as intermediary elements that create feedback paths to compensate for voltage drops across force switches. These sense switches act as mediators that detect voltage errors and enable correction through the feedback mechanism, allowing smaller force switches to be used without sacrificing linearity.
2Manufacturing precision
If large CMOS switches are used to reduce switch resistance, then INL error decreases, but parasitic capacitance increases
Solution Approach 1:
By segmenting the switching function into force and sense components, the patent reduces the size requirement for individual switches. Smaller switches inherently have lower parasitic capacitance, so the segmented architecture naturally reduces total parasitic capacitance while maintaining the low resistance needed for accurate switching.
3Manufacturing precision
If large CMOS switches are used to reduce switch resistance, then voltage drops decrease, but leakage current increases particularly at high temperature
Solution Approach 1:
The separation of force and sense switches allows optimization of each for its specific role. Force switches can be sized appropriately for current handling while sense switches are optimized for voltage sensing with minimal leakage. This segmentation reduces total leakage current compared to using one large switch for both functions.
4Area of stationary object
If smaller CMOS switches are used to reduce silicon area, then miniaturization improves, but switch resistance increases and INL error increases
Solution Approach 1:
The patent successfully uses smaller switches by segmenting the switching function. The force switches can be smaller than a single large switch would need to be, and the sense switches are even smaller since they only need to sense voltage. Together, this segmented approach achieves area reduction while maintaining precision through the feedback mechanism.
Solution Approach 2:
The sense switches create feedback paths that allow the circuit to detect and compensate for voltage drops across the force switches. This feedback mechanism enables the use of smaller switches with higher resistance without sacrificing INL performance, as the feedback actively corrects for the increased resistance effects.
5Speed
If smaller CMOS switches are used to reduce parasitic capacitance, then speed improves, but transition currents increase when loading new digital codes
Solution Approach 1:
By using smaller segmented switches instead of one large switch, the total parasitic capacitance is reduced, enabling faster switching. The transition current issue is managed by the distributed nature of the smaller switches, which share the switching burden and reduce peak current demands on any single device.
Data Source
AI summary
A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell. When an op amp drives particular cells, sense switches generate multiple a feedback paths to the driving op amp, which permits the op amp to drive the selected cell resistors at voltages that overcomes any voltage losses induces by associated force switches, and cancels the effect of any variation in the voltage losses induced by different force switches. The switch-controlled cells find application in a variety of DAC architectures, including binary weighted R2R architectures, equally-weighted segmented architectures or hybrid architectures that blend principles of R2R and segmented architectures.