DAC Sub-Segment Correction for INL Linearity and DNL Monotonicity
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Solution Overview
Problem
Digital-to-analog converters (DACs) face challenges in ensuring monotonicity and linearity, particularly in control loops, due to issues with Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL), where large look-up tables are required for correction and INL optimization can result in non-monotonic DACs.
Innovation Solution
The method involves off-line testing to determine INL and DNL values for sub-segments of a DAC, generating correction codes to improve linearity and ensure monotonicity by using extra bits of resolution to remap digital input codes, storing these codes in non-volatile memory for access during conversions, and applying them to produce an N+M bit digital output code that ensures all DNL values are greater than -1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large look-up table is used to correct INL and improve linearity, then the linearity of the DAC is improved, but the device complexity and memory requirements increase significantly
Solution Approach 1:
The patent divides the N-bit input code space into multiple sub-segments, and creates separate look-up tables for each sub-segment. This segmentation allows each LUT to be much smaller than a full N-bit LUT, while collectively covering the entire input range. The correction is applied by first identifying which sub-segment the input code belongs to, then applying the appropriate sub-segment correction.
Solution Approach 2:
The patent extracts only the most significant bits (MSBs) of the input code to select the appropriate sub-segment correction. By using only the MSBs for LUT selection and applying corrections based on sub-segment characteristics, the patent avoids storing complete N-bit correction tables, significantly reducing memory requirements while maintaining correction effectiveness.
2Manufacturing precision
If INL correction is applied to optimize linearity, then the INL performance is improved, but the DAC may become non-monotonic resulting in DNL values less than -1 LSB
Solution Approach 1:
The patent performs preliminary characterization and correction code generation during off-line testing before the DAC is deployed. The correction codes are pre-calculated to simultaneously satisfy both INL optimization and monotonicity requirements. This preliminary action ensures that when the correction is applied during normal operation, both linearity and monotonicity are maintained without requiring real-time complex calculations.
Solution Approach 2:
The patent modifies the correction approach by using sub-segment-based corrections with M extra bits of resolution. This parameter change allows the system to remap at least some of the 2^N possible digital input codes to more than 2^N possible digital output codes, providing enough flexibility to maintain both improved INL and guaranteed monotonicity (DNL > -1) simultaneously.
3Reliability
If M extra bits of resolution are used to remap digital input codes to ensure monotonicity, then the monotonicity is guaranteed, but the device complexity increases due to additional correction code storage and processing
Solution Approach 1:
The patent segments the correction process into two parts: sub-segment identification using MSBs and application of pre-calculated correction codes. This segmentation simplifies the processing logic compared to a monolithic correction approach, as each sub-segment has its own dedicated correction table that can be independently accessed and applied.
Solution Approach 2:
The patent performs all complex remapping and correction code generation during off-line testing before the DAC is deployed. The M extra bits of resolution and the corresponding correction codes are pre-calculated to ensure monotonicity. During normal operation, the system only needs to perform simple table lookups and code additions, significantly reducing real-time processing complexity.
Data Source
AI summary
INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the plurality of sub-segments for which INL values were determined, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to thereby ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.