DAC Code Remapping for INL Correction and Monotonic DNL
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Solution Overview
Problem
Digital-to-analog converters (DACs) face challenges in ensuring monotonicity and linearity, particularly in control loops, due to issues with Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL), where large look-up tables are required for correction and INL optimization can result in non-monotonic DACs.
Innovation Solution
The method involves off-line testing to determine INL and DNL values for sub-segments of a DAC, generating correction codes to improve linearity and ensure monotonicity by using extra bits of resolution to remap digital input codes, storing these codes in non-volatile memory for access during conversions, and employing look-up tables to select and apply correction codes to maintain DNL greater than -1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large look-up table is used to correct INL and improve linearity, then the linearity of the DAC is improved, but the device complexity and memory requirements increase significantly
Solution Approach 1:
The patent divides the N-bit DAC transfer function into multiple sub-segments and determines INL values for each sub-segment separately. This segmentation allows correction codes to be generated for smaller ranges, reducing the overall complexity of the correction mechanism while maintaining comprehensive linearity improvement across the full DAC range.
Solution Approach 2:
The patent changes the parameter representation by using correction codes that remap input codes rather than storing complete correction tables. By transforming the correction approach from direct voltage compensation to code remapping, the system achieves linearity correction with reduced memory requirements and simplified hardware.
2Manufacturing precision
If INL correction is applied to improve linearity, then the accuracy is improved, but the DAC may become non-monotonic resulting in DNL values less than -1 LSB
Solution Approach 1:
The patent performs preliminary determination of both INL and DNL values during off-line testing before final correction code generation. By anticipating potential monotonicity issues in advance and incorporating DNL constraints into the correction code determination process, the system ensures monotonicity is maintained while achieving linearity correction.
Solution Approach 2:
The patent incorporates feedback by using the determined DNL values to adjust and validate the correction codes. The correction process includes checking that DNL remains greater than -1 LSB, and using this information to refine the correction codes, ensuring that monotonicity is preserved while improving linearity.
3Reliability
If extra bits of resolution are used to remap digital input codes to ensure monotonicity, then the monotonicity is improved, but the device complexity increases
Solution Approach 1:
The patent adds an extra dimension to the code space by utilizing M extra bits of resolution beyond the original N bits. This dimensional expansion allows the system to remap codes in a way that ensures monotonicity without requiring complex control logic, as the additional bits provide the necessary degrees of freedom for code redistribution.
Data Source
AI summary
INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.