DAC Jitter Correction Circuit for High-Fidelity Audio Conversion
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Solution Overview
Problem
Conventional methods for converting digital audio to analog face a trade-off between higher fidelity, which requires higher performance Phase Locked Loops (PLLs) with increased cost and power consumption, and lower fidelity options that reduce cost and power but compromise on signal quality due to higher clock signal jitter.
Innovation Solution
A digital correction circuit comprising a time-to-digital converter, linear predictor, mixer, and subtractor is used to generate a pre-distorted signal that compensates for clock signal jitter, improving the fidelity of the analog output while reducing the need for high-performance PLLs and associated costs and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a higher performance PLL is used to reduce clock signal jitter and improve audio fidelity, then the fidelity and signal-to-noise ratio are improved, but the cost and power consumption increase
Solution Approach 1:
The patent extracts the jitter compensation function from the PLL circuit itself and implements it separately through a correction circuit that processes the DAC output signal. This allows the use of a lower-performance, lower-power PLL while still achieving high audio fidelity through post-processing correction of jitter effects.
Solution Approach 2:
The patent introduces a correction circuit as an intermediary component between the DAC and audio output. This correction circuit acts as a mediator that compensates for PLL-induced jitter without requiring the PLL itself to be high-performance, thereby decoupling the power consumption from the fidelity requirement.
2Measurement precision
If a higher performance PLL is used to reduce clock signal jitter and improve audio fidelity, then the signal-to-noise ratio is improved, but the device complexity and cost increase
Solution Approach 1:
The patent extracts the jitter compensation functionality from the complex high-performance PLL and implements it as a separate correction circuit with simpler architecture. This separation allows each component to be optimized independently, reducing overall system complexity while maintaining high signal-to-noise ratio.
Solution Approach 2:
The patent segments the audio processing system into distinct functional blocks: a simple PLL for clock generation and a separate correction circuit for jitter compensation. This segmentation allows the use of a low-complexity PLL while achieving high fidelity through the dedicated correction stage.
3Use of energy by moving object
If a lower performance PLL is used to reduce cost and power consumption, then the cost and power consumption are decreased, but the audio fidelity and signal quality deteriorate due to higher clock signal jitter
Solution Approach 1:
The patent converts the harmful effect of clock jitter into a benefit by designing a correction circuit that specifically targets and compensates for jitter-induced distortions. The correction circuit uses the jittered signal as input and produces a corrected output, effectively turning the PLL's weakness into an opportunity for targeted correction.
Solution Approach 2:
The correction circuit performs preliminary compensation for expected jitter effects before the signal is fully processed and output. By anticipating and correcting for PLL-induced jitter in advance, the system maintains high audio fidelity even though the PLL itself is low-performance and low-power.
4Ease of manufacture
If a lower performance PLL is used to reduce cost and complexity, then the device cost is decreased, but the audio fidelity deteriorates due to higher clock signal jitter
Solution Approach 1:
The patent extracts the fidelity-critical jitter compensation function from the expensive high-performance PLL and implements it as a separate, potentially more cost-effective correction circuit. This allows manufacturers to use cheaper PLLs while maintaining high audio fidelity through the correction stage.
Solution Approach 2:
The correction circuit serves as a cost-effective substitute for expensive high-performance PLLs. Rather than investing in a costly PLL with inherent low jitter, the system uses a cheap PLL combined with a correction circuit that achieves the same effective result at lower overall cost.
Data Source
AI summary
A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.