Dual Resistor Ladder DAC Level Shifting for Higher Resolution
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Solution Overview
Problem
Existing dual resistor ladder digital-to-analog converters (DACs) face challenges in increasing resolution without degrading operating speed and increasing output impedance and capacitance, and struggle with matching resistive elements across fabrication processes and temperatures, leading to substantial degradation in differential nonlinearity (DNL) and integral nonlinearity (INL) performance.
Innovation Solution
The implementation of a dual resistor ladder DAC with a coarse ladder and a fine ladder of series-connected MOS transistors, where parallel-connected MOS bit-shifting transistors are used to achieve improved resolution and accuracy without increasing the number of resistors, by ensuring precise matching of channel resistances across different fabrication processes and temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of resistors in the coarse or fine ladder is doubled to increase DAC resolution by 1 bit, then the resolution is improved, but the impedance and parasitic capacitance of the ladders double, degrading operating speed
Solution Approach 1:
The patent changes the physical state of the fine ladder resistors by implementing them as MOS transistors operating in the triode region rather than traditional poly resistors. This parameter change allows the resistance values to be dynamically controlled through gate voltages, enabling resolution enhancement without proportionally increasing the physical resistor count and associated parasitic elements.
Solution Approach 2:
The patent introduces dynamic control of the fine ladder elements through MOS transistor gate voltages, allowing the effective resistance values to be adjusted programmatically. This dynamic approach replaces static resistor values with controllable impedance, enabling resolution improvement through digital control rather than physical resistor multiplication.
2Measurement precision
If the number of resistors is doubled to increase DAC resolution, then the resolution is improved, but the silicon area cost increases
Solution Approach 1:
By changing the implementation from fixed poly resistors to MOS transistors in the triode region, the patent achieves variable resistance values without requiring proportional increases in physical component count. The MOS transistor's resistance is controlled by gate voltage rather than physical dimensions, reducing area requirements for achieving higher resolution.
3Ease of manufacture
If traditional poly resistors are used in the fine ladder, then the circuit is simple to manufacture, but there is substantial degradation in DNL and INL performance across fabrication processes and temperatures
Solution Approach 1:
The patent changes the fine ladder implementation from temperature-sensitive poly resistors to MOS transistors operating in the triode region. This parameter change exploits the MOS transistor's electrical characteristics, where resistance is controlled by gate voltage rather than being fixed by physical dimensions. This provides immunity to process and temperature variations that affect poly resistor values, dramatically improving DNL and INL performance.
Solution Approach 2:
The patent replaces the passive mechanical/resistive system (poly resistors) with an active electronic system (MOS transistors controlled by gate voltages). This substitution allows electrical control of resistance values, replacing the fixed physical properties of poly resistors with controllable electronic parameters that are immune to fabrication process variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the resolution and accuracy of the DAC while maintaining operating speed, significantly improving DNL and INL performance over a range of process and temperature variations without increasing output impedance and capacitance.
Implementation Method 1
use of series-connected MOSFETs operating in their deep triode regions as resistive elements in the fine ladder section of a dual resistor ladder
Implementation Method 2
ensuring precise matching of channel resistances across different fabrication processes and temperatures
Data Source
AI summary
A dual resistor ladder DAC includes a coarse ladder including a plurality of coarse ladder resistors and a fine ladder including a plurality of MOS transistors coupled between first and second conductors. A first group of parallel-connected bit-shifting transistors is coupled between the first and third conductors. A second group of parallel-connected MOS bit-shifting transistors is coupled between the third and top conductors. A third group of parallel-connected bit-shifting transistors is coupled between bottom and fourth conductors. A fourth group of parallel-connected bit-shifting transistors is coupled between the second and fourth conductors. Parallel-connected bit-shifting transistors are turned either on or off in response to a plurality of bit-switching bits of a binary number to be converted. One of the bottom, first, second, third, and top conductors is coupled to a DAC output conductor in response to the plurality of bit-switching bits.