Current-Steering DAC Load Matching for Timing Skew Reduction

The patent introduces dummy transistors as intermediary elements connected to the driver outputs. These dummy transistors act as mediators that balance the capacitive loads across different current-steering segments, thereby reducing timing skew errors while preserving the high-speed conversion capability. The dummy transistors are strategically placed to match the total capacitance at each driver output, including both the current-steering transistors and dummy transistors.

The patent modifies the capacitive load parameters at each driver output by adding dummy transistors with specific gate widths. The gate width of each dummy transistor is carefully calculated to achieve capacitance matching. For example, if the first current-steering transistor has a larger gate width than the second, the dummy transistors are sized to compensate for this difference, ensuring that the total capacitance at both driver outputs is equal. This parameter adjustment approach reduces timing skew without requiring fundamental architectural changes.