DAC Logic Control Circuit With Merged Transistors for Faster Switching

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Solution Overview

Problem

Existing digital-to-analog converters (DACs) face challenges in achieving high switching speed and reduced transistor load due to the increasing demand for higher data rates and resolution, particularly in current steering DACs with return-to-zero (RTZ) and multi-path architectures, where multiple logic control signals are required to control differential switch pairs.

Innovation Solution

A logic control circuit design that merges transistors to reduce the total number of transistors while maintaining functionality, using a first and second logic cell with parallel and series-connected transistors of opposite carrier types, forming logic gates, thereby reducing parasitic capacitance and enhancing switching speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple logic control signals are used to control differential switch pairs in RTZ and multi-path DAC architectures, then the desired output voltage value of zero can be achieved, but the switching speed decreases and transistor load increases

Engineering Contradiction:
Improveoutput voltage precisionVSAvoidswitching speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent merges multiple logic control signals into a single logic control signal by combining multiple current steering units under one differential switch pair. This consolidation reduces the number of transistors and logic cells required, thereby decreasing parasitic capacitance and improving switching speed while maintaining the ability to achieve zero output voltage through the coordinated operation of the merged units

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If the number of current steering units is increased to achieve higher resolution, then the data rate and precision improve, but the load on logic cells doubles and switching speed decreases

Engineering Contradiction:
ImproveresolutionVSAvoidlogic cell load
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple current steering units under a single differential switch pair, allowing multiple units to be controlled by one logic control signal. This reduces the number of logic cells and transistors required, decreasing the load on remaining logic components and improving switching speed while maintaining high resolution through the combined current steering capability of multiple units

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The differential switch pair is designed to control multiple current steering units simultaneously, making it a universal control element that serves multiple functions. This multi-functional approach allows a single logic control signal to manage several current steering units, reducing overall circuit complexity while maintaining high resolution performance

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4645704A1A logic control circuit for use in a digital-to-analog converter
Publication Date: 2025.11.05 SCALINX
  • EP4645704A1 patent drawingFigure 1A~1B
  • EP4645704A1 patent drawingFigure 2~3B
  • EP4645704A1 patent drawingFigure 4A~4B

AI summary

A logic control circuit for a digital-to-analog converter, comprising: a first logic cell and a second logic cell each comprising: a first input terminal, a second input terminal and an output terminal; a first transistor and a second transistor both of a first carrier type, wherein the first transistor and the second transistor are connected in parallel; and a third transistor of a second carrier type opposite to the first carrier type; wherein the drain terminals of the first transistor, the second transistor, and the third transistor are connected to the output terminal; and a fourth transistor of the second carrier type connected in series with the third transistors of the first logic cell and the second logic cell such that the first logic cell and the fourth transistor form a first logic gate and the second logic cell and the fourth transistor form a second logic gate.