DAC Multiplexer Circuit With Clock Synchronization for SFDR
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Solution Overview
Problem
Conventional half-rate multiplexers for digital to analog converter (DAC) based transmitters suffer from undesirable tone close to half of the sampling frequency, limiting spurious-free dynamic range (SFDR) and effective number of bits (ENOB), and data quality degradation at high sampling frequencies due to duty cycle errors and intersymbol interference.
Innovation Solution
A multiplexer circuit with symmetrical data input paths driven by a half-rate clock signal, utilizing a clock synchronizer to synchronize the half-rate clock with a full-rate clock, and implementing a full-rate multiplexer architecture with flip-flops to minimize duty cycle errors and reduce intersymbol interference, while maintaining high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional half-rate multiplexer is used, then the circuit complexity is reduced, but spurious-free dynamic range and effective number of bits are limited due to undesirable tones near Fs/2
Solution Approach 1:
The multiplexer is divided into multiple stages (first stage multiplexer and second stage multiplexer) with different sampling rates. The first stage operates at full rate while the second stage operates at half rate, segmenting the signal processing function to eliminate spurious tones while maintaining circuit efficiency.
Solution Approach 2:
A clock synchronizer is introduced as an intermediary component between the half-rate clock source and the multiplexer stages. This synchronizer aligns the clock phases and reduces systematic duty cycle errors, thereby improving spurious-free dynamic range without significantly increasing overall system complexity.
2Device complexity
If a conventional half-rate multiplexer is used, then the circuit complexity is reduced, but effective number of bits is limited due to systematic duty cycle errors
Solution Approach 1:
The multiplexer is divided into multiple stages (first stage multiplexer and second stage multiplexer) with different sampling rates. The first stage operates at full rate while the second stage operates at half rate, segmenting the signal processing function to eliminate spurious tones while maintaining circuit efficiency.
Solution Approach 2:
A clock synchronizer is introduced as an intermediary component between the half-rate clock source and the multiplexer stages. This synchronizer aligns the clock phases and reduces systematic duty cycle errors, thereby improving spurious-free dynamic range without significantly increasing overall system complexity.
3Speed
If a half-rate clock signal is used, then the operating speed is reduced, but data quality is maintained, however spurious tones appear near half the sampling frequency
Solution Approach 1:
The multiplexer is divided into multiple stages (first stage multiplexer and second stage multiplexer) with different sampling rates. The first stage operates at full rate while the second stage operates at half rate, segmenting the signal processing function to eliminate spurious tones while maintaining circuit efficiency.
Solution Approach 2:
The sampling rate parameter is changed dynamically across different stages of the multiplexer. The first stage uses full-rate sampling while the second stage uses half-rate sampling, allowing the system to achieve both high speed operation and suppression of spurious tones through parameter variation.
4Productivity
If the sampling frequency is increased, then the data transfer speed is improved, but data quality is degraded due to intersymbol interference
Solution Approach 1:
The multiplexer is divided into multiple stages (first stage multiplexer and second stage multiplexer) with different sampling rates. The first stage operates at full rate while the second stage operates at half rate, segmenting the signal processing function to eliminate spurious tones while maintaining circuit efficiency.
Solution Approach 2:
The system uses periodic clock signals with different frequencies (full-rate and half-rate clocks) to drive different stages of the multiplexer. This periodic action with carefully selected frequencies allows high-speed data transfer while preventing intersymbol interference through synchronized switching operations.
Data Source
AI summary
Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data.