Current-Steering DAC Offset Calibration for Carrier Suppression
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Solution Overview
Problem
Current digital-to-analog converters (DACs) suffer from direct-current (DC) offset issues that impact system specifications such as carrier suppression and local oscillator leakage, which are not adequately addressed by existing technologies.
Innovation Solution
A digital-to-analog converter (DAC) circuit with a decoder, current-steering cells, an offset detection circuit, and a digital controller, utilizing a comparator and calibration DACs to detect and correct DC offsets through a binary search algorithm, ensuring accurate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DAC circuits are used without offset correction, then the device complexity remains low, but DC offsets cause poor carrier suppression and local oscillator leakage
Solution Approach 1:
The patent applies preliminary action by performing DC offset calibration before normal DAC operation. The calibration mode detects and corrects DC offsets in advance using a comparator and calibration DACs, ensuring that the main DAC operates without offset errors during normal mode, thereby improving carrier suppression without adding continuous complexity
Solution Approach 2:
The patent extracts the DC offset correction function as a separate calibration subsystem including calibration DACs and a comparator. This isolated calibration path handles offset correction independently from the main signal path, allowing the main DAC to maintain simplicity while the extracted calibration subsystem addresses the reliability issue
2Reliability
If traditional DAC circuits are used without offset correction, then the device complexity remains low, but local oscillator leakage is not adequately suppressed
Solution Approach 1:
The calibration process performs preliminary correction of DC offsets that cause local oscillator leakage before the DAC is used for normal operation. By detecting and correcting offsets in advance through the comparator-based calibration mode, the system suppresses local oscillator leakage effectively without requiring continuous complex correction mechanisms
3Measurement precision
If calibration DACs and offset detection circuit are added, then DC offset accuracy is improved, but hardware overhead increases
Solution Approach 1:
The patent uses partial action by applying calibration only to the DC offset component rather than the entire signal range. The calibration DACs and comparator are engaged only during calibration mode to correct offset errors, while the main DAC handles full-scale signal conversion during normal operation, achieving high DC offset accuracy without excessive hardware overhead
4Measurement precision
If calibration DACs and offset detection circuit are added, then DC offset accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by performing DC offset calibration only during initialization or at scheduled intervals rather than continuously. The calibration mode with comparator and calibration DACs is activated periodically to update offset corrections, while the main DAC operates in normal mode between calibrations, achieving high DC offset accuracy while minimizing power consumption
Data Source
AI summary
Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.