DAC Ramp-Down Control for Switching Converter Undershoot
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Solution Overview
Problem
Switching regulators face significant challenges in minimizing undershoot of the output voltage during ramp-down, particularly under light-load conditions, which can lead to errors and noise in digital systems and flicker in electronic components.
Innovation Solution
The implementation of DAC control logic that decrements the DAC input code in a series of steps, waiting until at least one switching cycle has occurred before making changes, and adjusting the DAC clock rate to reduce undershoot while maintaining efficient ramp-down time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the DAC input code is decremented continuously during ramp-down, then the ramp-down time is reduced, but the output voltage undershoot increases
Solution Approach 1:
The patent segments the DAC code decrement process into discrete steps synchronized with switching cycles. Instead of continuous decrementing, the DAC code is decremented in discrete steps at specific switching cycle boundaries, which segments the voltage transition into controlled phases that prevent undershoot while maintaining reasonable ramp-down speed.
Solution Approach 2:
The patent implements preliminary action by predicting when the output voltage will reach the target value based on the current decrement rate and remaining steps. The system calculates ahead of time when to slow down or pause the decrement process to ensure the voltage settles exactly at the target without overshooting or undershooting, preventing the harmful effect before it occurs.
2Speed
If the DAC clock rate is increased to speed up voltage adjustment, then the response time is reduced, but the undershoot during ramp-down worsens
Solution Approach 1:
The patent applies dynamics by making the DAC clock rate variable rather than fixed. The system dynamically adjusts the clock rate based on the ramp-down phase: using higher rates during initial transitions for speed, then automatically reducing the rate as the voltage approaches the target to prevent undershoot. This dynamic adaptation allows the system to optimize both speed and stability at different stages of the voltage transition.
3Loss of time
If the DAC code is decremented in larger steps, then the ramp-down time is reduced, but the voltage precision and control accuracy decrease
Solution Approach 1:
The patent implements local quality by varying the decrement step size based on the local operating condition - specifically, the proximity to the target voltage. During early ramp-down phases when the voltage is far from target, larger steps are used for faster convergence. As the voltage approaches the target, the step size automatically reduces to smaller values, ensuring precise settling without undershoot. This local adaptation of step quality optimizes both speed and precision at different stages.
Data Source
AI summary
DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.