Current-Steering DAC Randomized Switching for Lower Harmonic Distortion
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Solution Overview
Problem
Digital-to-analog converters experience significant harmonic distortion during signal conversion, leading to reduced spurious-free dynamic range (SFDR) due to errors in the conversion process.
Innovation Solution
The digital-to-analog converter incorporates a clock driver, decoders, a current source matrix, and pseudo random mode generators coupled with multiplexers to randomly select and output signals, averaging errors and reducing harmonic distortion by controlling the output sequence of signals to the current source matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a digital-to-analog converter is coupled to a plurality of signal lines for converting signals, then signal conversion capability is improved, but harmonic distortion increases significantly
Solution Approach 1:
The patent applies dynamics by making the signal path selection variable and random rather than fixed. The pseudo-random mode generator dynamically changes the selection sequence of signal lines, causing the harmonic distortion to vary randomly in magnitude and phase. This dynamic approach transforms the deterministic distortion into a stochastic process that can be averaged out, resolving the contradiction between maintaining signal conversion capability and reducing harmonic distortion.
Solution Approach 2:
The patent employs periodic action through the use of a clock driver that generates periodic clock signals to control the pseudo-random mode generator. This periodic control structure ensures that the signal line selection follows a repeatable pseudo-random sequence, allowing the system to maintain signal conversion functionality while systematically varying the distortion characteristics over time to achieve error averaging.
2Productivity
If signal conversion is performed using multiple signal lines, then conversion throughput is improved, but spurious-free dynamic range is reduced
Solution Approach 1:
The patent implements a feedback mechanism where the output signals from multiple signal lines are combined and processed through a feedback loop that includes the pseudo-random mode generator. The feedback structure allows the system to continuously adjust the signal line selection based on the accumulated error, creating a closed-loop system that maximizes throughput while maintaining spurious-free dynamic range through adaptive error cancellation.
Data Source
AI summary
A digital-to-analog converter includes a clock driver, a first decoder, a second decoder, a current source matrix, a pseudo random mode generator and at least one multiplexer. The first decoder and the second decoder are coupled to the clock driver. The current source matrix is coupled to the first decoder, and the pseudo random mode generator is used to randomly output a set of selecting signals. Each multiplexer of the at least one multiplexer includes a plurality of input ends coupled to a plurality of output ends of the second decoder, an output end coupled to the current source matrix, and a select end coupled to the pseudo random mode generator for controlling the output end to output a bit signal inputted from the input ends of the multiplexer according to one selecting signal of the set of selecting signals.