DAC Refresh Clock Gating for Low-Power Reference Retention
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Solution Overview
Problem
Digital-to-analog converter (DAC) circuits consume high dynamic power due to the continuous operation of their digital portions for maintaining reference voltages, leading to increased power consumption.
Innovation Solution
A refresh circuit is introduced to clock gate the DAC circuit's clock signal only when necessary, using a lower frequency timer to enable periodic refreshes independently of conversion operations, allowing the digital portion to be powered off between refresh intervals and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the digital portion of the DAC circuit is kept in full operation to perform periodic refresh of the reference voltage, then the reference voltage can be maintained, but the DAC circuit consumes an undesirably high amount of dynamic power
Solution Approach 1:
The patent implements periodic refresh operations where the digital portion of the DAC circuit is activated only at scheduled intervals to refresh the reference voltage, rather than operating continuously. A refresh circuit generates periodic refresh triggers that clock-ungate the digital portion temporarily, allowing it to perform conversion operations only when needed to maintain the reference voltage on the storage element.
Solution Approach 2:
The patent dynamically controls the operational state of the digital portion by using clock gating mechanisms. The digital portion transitions between active and inactive states based on refresh triggers, allowing the system to adapt its power consumption levels while maintaining reference voltage integrity through periodic updates.
2Use of energy by moving object
If the digital portion is powered off to reduce power consumption, then dynamic power usage decreases, but the reference voltage cannot be refreshed periodically
Solution Approach 1:
The patent uses a storage element (capacitor) to preliminarily store the reference voltage before the digital portion is powered off. This allows the reference voltage to be maintained during the inactive period without requiring continuous digital operation, enabling the digital portion to be powered off between refresh intervals while preserving the reference voltage.
Solution Approach 2:
The refresh circuit generates periodic refresh triggers that reactivate the digital portion at scheduled intervals. This periodic activation ensures the reference voltage is refreshed before it degrades, maintaining reliability while allowing the digital portion to remain powered off for extended periods between refreshes.
3Productivity
If the clock signal is continuously provided to the DAC circuit, then the digital portion can operate without interruption, but power consumption increases
Solution Approach 1:
The patent extracts the essential function of reference voltage maintenance from continuous operation by implementing periodic refresh. The clock signal is removed (gated) from the digital portion between refresh operations, taking out the unnecessary continuous operation while preserving the essential refresh function that maintains reference voltage integrity.
Solution Approach 2:
The clock signal is provided periodically rather than continuously through clock gating controlled by refresh triggers. The digital portion receives the clock signal only during brief intervals when refresh operations are performed, reducing overall power consumption while maintaining the ability to perform conversion operations when needed.
Data Source
AI summary
In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.