DAC Reset Voltage Compensation for Idle Tone Suppression
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Solution Overview
Problem
Electronic products, such as audio devices, suffer from noise and idle tones during operation, leading to unintended sound output even when no sound is input, affecting their functionality and user experience.
Innovation Solution
A digital-to-analog converter with a compensation circuit that adjusts the voltage level of the reset analog signal during return-to-zero conversion, ensuring the voltage level is higher or lower than the initial reset level, thereby eliminating idle tones by generating an offset voltage beyond human audible range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If return-to-zero conversion is performed without voltage level compensation, then the circuit operation is simple, but idle tones are generated within the human audible range
Solution Approach 1:
The patent changes the voltage level parameter of the reset signal from a conventional level (e.g., 0V or ground) to a compensated level that is higher or lower than the initial reset level. This parameter change shifts the idle tone frequency beyond the human audible range (above 20kHz), thereby eliminating the harmful effect while maintaining circuit simplicity. The compensation circuit adjusts the reset voltage level dynamically to achieve this frequency shift.
Solution Approach 2:
The patent converts the harmful idle tones within the audible range into beneficial high-frequency signals beyond human hearing. By compensating the reset voltage level, the idle tones are shifted to frequencies above 20kHz, which are inaudible to humans. This transforms a harmful auditory disturbance into an imperceptible high-frequency signal, effectively eliminating the problem while utilizing the same return-to-zero conversion mechanism.
2Object-affected harmful factors
If the reset voltage level is increased to suppress idle tones, then idle tones are eliminated, but the power consumption increases
Solution Approach 1:
The patent applies partial compensation rather than full-level resetting. The compensation circuit adds only the necessary voltage offset to shift the idle tone frequency beyond the audible range, rather than using excessive voltage levels. This partial action achieves the goal of eliminating audible idle tones while minimizing the increase in power consumption, as the compensation voltage is precisely controlled to be just sufficient for frequency shifting.
3Object-affected harmful factors
If a complex compensation circuit is added to adjust reset voltage levels, then idle tones are suppressed, but the device complexity increases
Solution Approach 1:
The patent introduces a compensation circuit as an intermediary component between the digital-to-analog conversion circuit and the output. This intermediary circuit specifically handles the voltage level compensation function, isolating the complexity from the main conversion circuitry. The compensation circuit uses simple voltage reference sources and switching elements to achieve the voltage level adjustment, thereby suppressing idle tones without significantly increasing overall device complexity.
Data Source
AI summary
A digital-to-analog converter and a digital-to-analog conversion method thereof are provided. The digital-to-analog conversion method includes: converting a digital data signal into an analog data signal in a first cycle according to a clock signal, resetting the analog data signal in a second cycle according to the clock signal and a reset signal corresponding to a first reset level, and compensating for a voltage level of the reset analog data signal in the second cycle according to a second reset level, so that the voltage level of the reset analog data signal is the second reset level. The second reset level is higher or lower than the first reset level.