Relative DAC Segment Calibration for Low DNL Linearity
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Solution Overview
Problem
High-speed digital-to-analog converter (DAC) devices experience non-linearity issues due to random mismatch in segments, which degrade wireline transmission performance.
Innovation Solution
A relative calibration method is employed to match the strengths of DAC segments iteratively without using absolute references, ensuring each segment's output is proportional to its predecessor, using a comparator and control logic to adjust segment strengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If segmented DAC architecture is used to reduce mismatch impacts, then linearity performance is improved, but device complexity increases due to additional segmentation and calibration requirements
Solution Approach 1:
The DAC is divided into multiple segments (first subset and second subset of DAC segments) that can be independently calibrated. This segmentation allows for targeted calibration of specific segments to reduce mismatch impacts while maintaining overall system manageability.
Solution Approach 2:
The calibration process is performed preliminarily during manufacturing or initialization. The control logic circuit pre-adjusts the relative strengths of DAC segments by tuning their output strengths to match reference values, storing these calibration values for later use during normal operation, thereby eliminating the need for real-time calibration complexity.
Solution Approach 3:
The calibration process uses feedback from the comparator device to iteratively adjust DAC segment strengths. The comparator compares actual segment output strengths against reference values, and the control logic uses this feedback information to tune the segments until matching is achieved, ensuring precise calibration without excessive complexity.
2Manufacturing precision
If iterative calibration of DAC segments is performed, then manufacturing precision is improved, but loss of time increases due to iterative adjustment process
Solution Approach 1:
The iterative calibration process is performed preliminarily during manufacturing or system initialization, not during normal operation. The calibration values are stored in memory for reuse, so the time-consuming iterative process occurs only once, establishing precise segment matching before the DAC enters production mode.
Solution Approach 2:
The calibration process uses periodic iterative adjustments where the control logic circuit systematically tunes each DAC segment in sequence, comparing against reference values and making adjustments in controlled steps. This periodic approach converges efficiently to the optimal calibration point without requiring continuous adjustment during operation.
3Device complexity
If relative calibration method is used without absolute references, then device complexity is reduced, but measurement precision may be affected
Solution Approach 1:
The comparator device serves as an intermediary that enables relative comparison between DAC segments without requiring absolute reference standards. By comparing segment outputs against each other through the comparator, the system achieves accurate relative calibration using only the segments themselves as references, eliminating the need for external absolute reference equipment.
Solution Approach 2:
The calibration process adjusts the output strength parameter of each DAC segment iteratively. The control logic circuit changes the strength parameter of segments in the second subset to match the reference strength values from the first subset, achieving precise relative calibration through parameter optimization rather than absolute measurement.
Data Source
AI summary
A system and method for calibrating a digital-to-analog converter (DAC) device. The method includes tuning a second subset of one or more DAC segments to match a strength of a first subset of DAC segments wherein the first subset of DAC segments is of a strength nominally equal to that of the second subset of DAC segments. The process is iterative, and the second subset of DAC segments is associated with lesser significant bits than the bits associated with the first subset of DAC segments. The process is repeated to tune each of successive second subsets of DAC segments to corresponding successive first subsets of DAC segments in top-down order from a segment associated with a MSB input to a segment associated with a LSB input. In each case the first subset of DAC segments is of a strength nominally equal to that of the second subset of DAC segments.