Digital-to-analog converter with segmented parallel processing
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Solution Overview
Problem
Existing digital-to-analog converters in display devices face challenges in achieving satisfactory operation speed and minimizing power consumption while providing stable analog signals to pixels, leading to noticeable supply processes and suboptimal image quality.
Innovation Solution
A digital-to-analog converter design that includes a converting unit generating first and second analog signals based on image data in different periods, with the first signal distributed sequentially and the second signal distributed in reverse sequential order, utilizing sub-converters with different driving frequencies and a switching unit to connect output stages with input stages of the distributing unit, and a sampling unit for temporal storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional digital-to-analog converter sequentially generates and distributes analog signals to all pixel columns, then the circuit structure is simple, but the operation speed is slow and power consumption is high
Solution Approach 1:
The patent divides the pixel columns into two groups: first pixel columns (odd-numbered) and second pixel columns (even-numbered). The digital-to-analog converter is correspondingly divided into a first digital-to-analog converter and a second digital-to-analog converter. This segmentation allows parallel processing of different pixel column groups, thereby increasing operation speed without requiring a complete redesign of the converter architecture.
Solution Approach 2:
The first digital-to-analog converter generates analog signals for the first pixel columns in advance during periods when the second pixel columns are being processed by the second converter. This preliminary action overlaps the operation timelines of the two converter groups, effectively doubling the throughput without proportionally increasing the time required for each individual conversion process.
2Productivity
If the digital-to-analog converter operates at high speed to meet display refresh rates, then the operation speed is satisfactory, but power consumption increases
Solution Approach 1:
By segmenting the converter into two independent digital-to-analog converters that process different pixel column groups, each converter can operate at a lower clock frequency while achieving the same overall data writing speed. This reduces dynamic power consumption which is proportional to the square of the frequency and the switching activity in the circuit.
Solution Approach 2:
The patent implements a periodic operation pattern where the first digital-to-analog converter operates during periods when the second converter is inactive, and vice versa. This alternating periodic action allows the system to maintain high productivity while each individual converter operates at lower power levels, reducing the peak power consumption of the overall system.
3Reliability
If the analog signals are supplied sequentially to pixel columns, then the circuit design is straightforward, but the supply process becomes noticeable and image quality deteriorates
Solution Approach 1:
The patent divides the pixel columns into two groups and uses separate digital-to-analog converters for each group. This segmentation enables simultaneous or overlapped generation and distribution of analog signals to different pixel column groups, making the supply process imperceptible to human vision and thereby improving image quality without requiring overly complex interleaved arbitration logic.
Solution Approach 2:
The patent introduces buffer circuits as intermediaries between the digital-to-analog converters and the pixel columns. These buffers hold the generated analog signals and release them at appropriate timing, smoothing out any residual temporal artifacts and ensuring uniform signal delivery across all pixel columns, which enhances image quality.
Data Source
AI summary
A digital-to-analog converter may include a converting unit and a distributing unit. The converting unit may generate a first analog signal set based on less-than-all bits of an image data set in a first period and may generate a second analog signal set based on all bits of the image data set in a second period. The all bits may include at least 2 bits. The distributing unit may include output terminals, may distribute the first analog signal set to the output terminals in a first sequence in the first period, and may distribute the second analog signal to the output terminals in a second sequence. The second sequence may be opposite to the first sequence.