Segmented Non-Binary DAC Self-Calibration for Linearity Correction

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Solution Overview

Problem

High precision DACs face significant non-linearities due to resistor-based voltage coefficients, especially at 18 bits or greater, which are difficult to calibrate and increase manufacturing costs.

Innovation Solution

A self-calibrating method for a segmented non-binary DAC, involving a thermometric weighted segment and a sub-binary weighted segment, calculates and applies scaling factors to correct for non-linearities by measuring cumulative and non-cumulative series of outputs, using an ADC for calibration and storing these factors for normal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high accuracy analog trimming procedures are used to improve DAC linearity, then manufacturing precision improves, but device complexity and manufacturing cost increase

Engineering Contradiction:
ImproveDAC linearityVSAvoidtrimming procedure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The system performs self-calibration by automatically measuring its own output characteristics and computing correction factors without external intervention. The calibration controller measures DAC outputs at various input codes, calculates scaling factors, and applies corrections autonomously, eliminating the need for manual analog trimming procedures and reducing manufacturing complexity

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The calibration process is performed during manufacturing or initialization before normal operation begins. Scaling factors are pre-calculated and stored in memory for use during operational phases, allowing the system to be prepared in advance rather than requiring complex real-time adjustments

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If resistor elements with voltage coefficients are used in DAC architecture, then ease of manufacture improves, but manufacturing precision deteriorates due to non-linearities

Engineering Contradiction:
ImproveDAC implementation easeVSAvoidDAC transfer curve linearity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The system measures the actual output of the DAC at multiple input codes and uses this feedback information to calculate scaling factors that compensate for non-linearities. The ADC measures the DAC output, and the calibration controller uses these measurements to determine correction factors that are applied to subsequent DAC operations, creating a closed-loop system that eliminates the need for precision resistors

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes the operational parameters by applying scaling factors to the DAC input codes based on measured performance characteristics. By dynamically adjusting the effective weight of each bit through calculated scaling factors, the system compensates for resistor voltage coefficient effects without requiring physical changes to the resistor elements

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4576580A1Self-calibrating digital to analog converter
Publication Date: 2025.06.25 NXP USA INC
  • EP4576580A1 patent drawingFigure 1
  • EP4576580A1 patent drawingFigure 2
  • EP4576580A1 patent drawingFigure 3

AI summary

The disclosure relates to self-calibration of non-linearity in a digital to analog converter (DAC). Example embodiments include a method for calibrating non-linearity of a segmented non-binary DAC (200) in a self-calibrating DAC system (500), the method comprising: providing a first cumulative series of calibration input digital signals to a thermometric weighted segment (200a) and measuring a corresponding first series of outputs of the DAC (200) with an ADC (504); providing a second non-cumulative series of calibration input digital signals to the thermometric weighted segment (200a) and measuring a second series of outputs of the DAC (200) with the ADC (504); calculating a first scaling factor for the first plurality of switches (T1-T15) and resistive elements (βR) by dividing each of the second series of outputs of the DAC (200) by a difference between adjacent ones of the first series of outputs of the DAC (200); calculating a second scaling factor for the second plurality of switches (D0-D17) from a sum of the first series of outputs of the DAC (200) divided by a measured output range of the DAC (200); and storing the first and second scaling factors in a memory module (508) of the self-calibrating DAC system (500) for applying to a digital input (Din) during normal operation of the DAC system (500).