DAC Switching Sequence Generation for Mismatch Noise Shaping
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Solution Overview
Problem
Existing mismatch-shaping circuits for digital-to-analog converters (DACs) are expensive and require hardware components like quantizers and accumulators, which are not efficient in addressing noise and non-linearity due to elemental mismatches.
Innovation Solution
A double-summed-to-zero (DSTZ) graph is used to create a finite state machine that generates a switching sequence for tree-structured second-order mismatch-shaping DACs, eliminating the need for expensive hardware components by scrambling capacitor or current-source connections, thus suppressing DAC noise within the signal band.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If quantizer and limiter are used to generate 2nd order sequences, then noise shaping capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the essential function of noise shaping from complex hardware components (quantizer, limiter, accumulator) and implements it through a simplified finite state machine that generates second-order shaped sequences using basic digital logic, thereby removing unnecessary complexity while preserving the noise suppression capability
Solution Approach 2:
The invention replaces expensive, complex hardware components with a more economical finite state machine implementation that achieves the same noise shaping function using simpler, cheaper digital logic elements, reducing overall device cost and complexity
2Measurement precision
If 3-state accumulator and M-state accumulator are used, then sequence generation accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent removes the accumulator hardware entirely and extracts the sequence generation function into a finite state machine that directly produces second-order shaped sequences through state transitions, maintaining accuracy while eliminating complex accumulative computation hardware
Solution Approach 2:
The invention substitutes the mechanical/computational accumulator system with a digital finite state machine approach, replacing complex sequential accumulation operations with pre-defined state transition logic that achieves the same mathematical function with simpler digital circuitry
3Reliability
If mismatch-shaping circuits are implemented with traditional methods, then noise suppression is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs a cost-effective finite state machine implementation using basic digital logic gates instead of expensive dedicated mismatch-shaping circuitry, achieving the same noise suppression performance through economical digital components that are cheaper to manufacture
Solution Approach 2:
The finite state machine is designed to generate second-order shaped sequences that can be applied to various DAC configurations and mismatch conditions, providing a universal solution that reduces manufacturing costs through design reuse and standardization
Data Source
AI summary
An embodiment of the present invention is a technique to design a DAC. A double-summed-to-zero (DSTZ) graph is created having a plurality of nodes linked by a plurality of directed branches. The DSTZ graph represents a finite state machine (FSM) that generates a sequence for a switching block used in a mismatch-shaping digital-to-analog converter (DAC). Each of the plurality of nodes represents a state in the FSM. The DSTZ graph has a total work function and a total potential energy summing to zero for a cycle traversal. A switching sequence is generated starting from a reference node in the plurality of nodes in response to an input sequence. The reference node has a zero potential energy.